Lines Matching +full:gpio +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atheros AR71XX/AR724X/AR913X GPIO API support
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
12 #include <linux/gpio/driver.h>
44 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) in ath79_gpio_read() argument
46 return readl(ctrl->base + reg); in ath79_gpio_read()
49 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, in ath79_gpio_write() argument
52 writel(val, ctrl->base + reg); in ath79_gpio_write()
56 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) in ath79_gpio_update_bits() argument
60 old_val = ath79_gpio_read(ctrl, reg); in ath79_gpio_update_bits()
64 ath79_gpio_write(ctrl, reg, new_val); in ath79_gpio_update_bits()
71 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); in ath79_gpio_irq_unmask() local
75 gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data)); in ath79_gpio_irq_unmask()
76 raw_spin_lock_irqsave(&ctrl->lock, flags); in ath79_gpio_irq_unmask()
77 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); in ath79_gpio_irq_unmask()
78 raw_spin_unlock_irqrestore(&ctrl->lock, flags); in ath79_gpio_irq_unmask()
83 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); in ath79_gpio_irq_mask() local
87 raw_spin_lock_irqsave(&ctrl->lock, flags); in ath79_gpio_irq_mask()
88 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); in ath79_gpio_irq_mask()
89 raw_spin_unlock_irqrestore(&ctrl->lock, flags); in ath79_gpio_irq_mask()
90 gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data)); in ath79_gpio_irq_mask()
95 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); in ath79_gpio_irq_enable() local
99 raw_spin_lock_irqsave(&ctrl->lock, flags); in ath79_gpio_irq_enable()
100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); in ath79_gpio_irq_enable()
101 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); in ath79_gpio_irq_enable()
102 raw_spin_unlock_irqrestore(&ctrl->lock, flags); in ath79_gpio_irq_enable()
107 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); in ath79_gpio_irq_disable() local
111 raw_spin_lock_irqsave(&ctrl->lock, flags); in ath79_gpio_irq_disable()
112 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); in ath79_gpio_irq_disable()
113 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); in ath79_gpio_irq_disable()
114 raw_spin_unlock_irqrestore(&ctrl->lock, flags); in ath79_gpio_irq_disable()
120 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); in ath79_gpio_irq_set_type() local
142 return -EINVAL; in ath79_gpio_irq_set_type()
145 raw_spin_lock_irqsave(&ctrl->lock, flags); in ath79_gpio_irq_set_type()
148 ctrl->both_edges |= mask; in ath79_gpio_irq_set_type()
149 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); in ath79_gpio_irq_set_type()
151 ctrl->both_edges &= ~mask; in ath79_gpio_irq_set_type()
159 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); in ath79_gpio_irq_set_type()
162 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type); in ath79_gpio_irq_set_type()
164 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity); in ath79_gpio_irq_set_type()
168 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); in ath79_gpio_irq_set_type()
170 raw_spin_unlock_irqrestore(&ctrl->lock, flags); in ath79_gpio_irq_set_type()
176 .name = "gpio-ath79",
190 struct ath79_gpio_ctrl *ctrl = in ath79_gpio_irq_handler() local
198 raw_spin_lock_irqsave(&ctrl->lock, flags); in ath79_gpio_irq_handler()
200 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); in ath79_gpio_irq_handler()
203 both_edges = ctrl->both_edges & pending; in ath79_gpio_irq_handler()
205 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); in ath79_gpio_irq_handler()
206 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, in ath79_gpio_irq_handler()
210 raw_spin_unlock_irqrestore(&ctrl->lock, flags); in ath79_gpio_irq_handler()
212 for_each_set_bit(irq, &pending, gc->ngpio) in ath79_gpio_irq_handler()
213 generic_handle_domain_irq(gc->irq.domain, irq); in ath79_gpio_irq_handler()
219 { .compatible = "qca,ar7100-gpio" },
220 { .compatible = "qca,ar9340-gpio" },
227 struct device *dev = &pdev->dev; in ath79_gpio_probe()
228 struct ath79_gpio_ctrl *ctrl; in ath79_gpio_probe() local
234 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in ath79_gpio_probe()
235 if (!ctrl) in ath79_gpio_probe()
236 return -ENOMEM; in ath79_gpio_probe()
244 oe_inverted = device_is_compatible(dev, "qca,ar9340-gpio"); in ath79_gpio_probe()
248 return -EINVAL; in ath79_gpio_probe()
251 ctrl->base = devm_platform_ioremap_resource(pdev, 0); in ath79_gpio_probe()
252 if (IS_ERR(ctrl->base)) in ath79_gpio_probe()
253 return PTR_ERR(ctrl->base); in ath79_gpio_probe()
255 raw_spin_lock_init(&ctrl->lock); in ath79_gpio_probe()
256 err = bgpio_init(&ctrl->gc, dev, 4, in ath79_gpio_probe()
257 ctrl->base + AR71XX_GPIO_REG_IN, in ath79_gpio_probe()
258 ctrl->base + AR71XX_GPIO_REG_SET, in ath79_gpio_probe()
259 ctrl->base + AR71XX_GPIO_REG_CLEAR, in ath79_gpio_probe()
260 oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, in ath79_gpio_probe()
261 oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, in ath79_gpio_probe()
269 if (device_property_read_bool(dev, "interrupt-controller")) { in ath79_gpio_probe()
270 girq = &ctrl->gc.irq; in ath79_gpio_probe()
272 girq->parent_handler = ath79_gpio_irq_handler; in ath79_gpio_probe()
273 girq->num_parents = 1; in ath79_gpio_probe()
274 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in ath79_gpio_probe()
276 if (!girq->parents) in ath79_gpio_probe()
277 return -ENOMEM; in ath79_gpio_probe()
278 girq->parents[0] = platform_get_irq(pdev, 0); in ath79_gpio_probe()
279 girq->default_type = IRQ_TYPE_NONE; in ath79_gpio_probe()
280 girq->handler = handle_simple_irq; in ath79_gpio_probe()
283 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); in ath79_gpio_probe()
288 .name = "ath79-gpio",
296 MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");