| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 123 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
198 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
208 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
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| D | rv730_dpm.c | 42 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
61 if (dividers.enable_post_div) in rv730_populate_sclk_value()
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
72 if (dividers.enable_post_div) in rv730_populate_sclk_value()
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
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| D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs, in rv6xx_program_engine_spread_spectrum()
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| D | rv770_dpm.c | 322 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
404 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
412 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
423 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
440 if (dividers.vco_mode) in rv770_populate_mclk_value()
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| D | cypress_dpm.c | 493 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
508 dividers.post_div = 1; in cypress_populate_mclk_value()
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
524 if (dividers.vco_mode) in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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| /linux-6.12.1/drivers/clk/baikal-t1/ |
| D | Kconfig | 12 configurable and fixed clock dividers. Enable this option to be able
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
31 bool "Baikal-T1 CCU Dividers support"
35 Enable this to support the CCU dividers used to distribute clocks
37 SoC. CCU dividers can be either configurable or with fixed divider,
38 either gateable or ungateable. Some of the CCU dividers can be as well
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | divider.txt | 28 Additionally an array of valid dividers may be supplied like so:
30 ti,dividers = <4>, <8>, <0>, <16>;
43 unless the divider array is provided, min and max dividers. Optionally
61 - ti,dividers : array of integers defining divisors
66 if ti,dividers is not defined.
68 only valid if ti,dividers is not defined.
70 only valid if ti,dividers is not defined.
114 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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| /linux-6.12.1/drivers/gpu/drm/amd/display/modules/color/ |
| D | color_gamma.c | 390 struct dividers { struct
1277 struct dividers dividers) in scale_gamma() argument
1313 dividers.divider1); in scale_gamma()
1315 dividers.divider1); in scale_gamma()
1317 dividers.divider1); in scale_gamma()
1322 dividers.divider2); in scale_gamma()
1324 dividers.divider2); in scale_gamma()
1326 dividers.divider2); in scale_gamma()
1331 dividers.divider3); in scale_gamma()
1333 dividers.divider3); in scale_gamma()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-div.yaml | 8 title: Baikal-T1 Clock Control Unit Dividers
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
26 3) AXI-bus clock dividers (AXI) - described in this binding file.
27 4) System devices reference clock dividers (SYS) - described in this binding
51 then passed over CCU dividers to create signals required for the target clock
52 domain (like AXI-bus or System Device consumers). The dividers have the
71 peculiarities the dividers may lack of some functionality depicted on the
76 The clock dividers, which output clock is then consumed by the SoC individual
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
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| D | baikal,bt1-ccu-pll.yaml | 19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
24 3) AXI-bus clock dividers (AXI).
25 4) System devices reference clock dividers (SYS).
73 the binding supports the PLL dividers configuration in accordance with a
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| D | dove-divider-clock.txt | 3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
4 high speed clocks for a number of peripherals. These dividers are part of
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| /linux-6.12.1/sound/soc/codecs/ |
| D | wm8510.h | 61 /* DAC clock dividers */
65 /* ADC clock dividers */
69 /* PLL Out dividers */
75 /* BCLK clock dividers */
83 /* MCLK clock dividers */
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| D | wm8940.h | 74 /* MCLK clock dividers */
84 /* BCLK clock dividers */
92 /* PLL Out Dividers */
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| D | wm8974.h | 59 /* PLL Out dividers */
65 /* BCLK clock dividers */
73 /* MCLK clock dividers */
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| D | wm8753.h | 87 /* PCM clock dividers */
96 /* BCLK clock dividers */
103 /* VXCLK clock dividers */
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| /linux-6.12.1/Documentation/devicetree/bindings/hwmon/ |
| D | adi,ltc4282.yaml | 51 adi,overvoltage-dividers:
53 Select which dividers to use for VDD Overvoltage detection. Note that
54 when the internal dividers are used the threshold is referenced to VDD.
63 adi,undervoltage-dividers:
65 Select which dividers to use for VDD Overvoltage detection. Note that
66 when the internal dividers are used the threshold is referenced to VDD.
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | ppatomctrl.c | 390 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong() argument
403 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
404 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
413 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi() argument
427 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
429 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
432 dividers->ul_fb_div.ul_fb_div_frac = in atomctrl_get_engine_pll_dividers_vi()
434 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
437 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
439 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
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| D | ppatomfwctrl.c | 244 * @param dividers output parameter:Clock dividers
248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-cpu.c | 48 * @rate_table: pll-rates and their associated dividers
103 /* alternate parent is active now. set the dividers */ in rockchip_cpuclk_set_dividers()
176 * the armclk speed is more than the old_rate until the dividers are in rockchip_cpuclk_pre_rate_change()
180 /* calculate dividers */ in rockchip_cpuclk_pre_rate_change()
189 * Change parents and add dividers in a single transaction. in rockchip_cpuclk_pre_rate_change()
192 * dividing the primary parent by the extra dividers that were in rockchip_cpuclk_pre_rate_change()
244 * post-rate change event, re-mux to primary parent and remove dividers. in rockchip_cpuclk_post_rate_change()
247 * primary parent by the extra dividers that were needed for the alt. in rockchip_cpuclk_post_rate_change()
263 /* remove dividers */ in rockchip_cpuclk_post_rate_change()
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| /linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_dw_hdmi.c | 17 #define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
19 #define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
23 u16 opmode_div; /* Mode of operation and PLL dividers */
25 u16 div; /* PLL dividers */
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-cpu.c | 160 * Helper function to set the 'safe' dividers for the CPU clock. The parameters
162 * dividers to be programmed.
218 * the values for DIV_COPY and DIV_HPM dividers need not be set. in exynos_cpuclk_pre_rate_change()
231 * the armclk speed is more than the old_prate until the dividers are in exynos_cpuclk_pre_rate_change()
232 * set. Also workaround the issue of the dividers being set to lower in exynos_cpuclk_pre_rate_change()
260 /* alternate parent is active now. set the dividers */ in exynos_cpuclk_pre_rate_change()
352 * the armclk speed is more than the old_prate until the dividers are in exynos5433_cpuclk_pre_rate_change()
353 * set. Also workaround the issue of the dividers being set to lower in exynos5433_cpuclk_pre_rate_change()
373 /* alternate parent is active now. set the dividers */ in exynos5433_cpuclk_pre_rate_change()
504 * the armclk speed is more than the old_prate until the dividers are in exynos850_cpuclk_pre_rate_change()
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 1000 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers() argument
1007 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1025 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1026 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1028 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1030 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1031 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1032 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1033 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1047 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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| /linux-6.12.1/sound/soc/pxa/ |
| D | pxa-ssp.h | 16 /* SSP audio dividers */
21 /* SSP ACDS audio dividers values */
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | polaris10_smumgr.c | 895 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
903 /* get the engine clock dividers for this clock value */ in polaris10_calculate_sclk_params()
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in polaris10_calculate_sclk_params()
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
909 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
913 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
914 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
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| D | vegam_smumgr.c | 724 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
732 /* get the engine clock dividers for this clock value */ in vegam_calculate_sclk_params()
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
738 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
742 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
743 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
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