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/linux-6.12.1/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
[all …]
Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mn-disp-blk-ctrl
21 - const: syscon
[all …]
/linux-6.12.1/drivers/spi/
Dspi-rzv2m-csi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Renesas RZ/V2M Clocked Serial Interface (CSI) driver
22 #define CSI_MODE 0x00 /* CSI mode control */
23 #define CSI_CLKSEL 0x04 /* CSI clock select */
24 #define CSI_CNT 0x08 /* CSI control */
25 #define CSI_INT 0x0C /* CSI interrupt status */
26 #define CSI_IFIFOL 0x10 /* CSI receive FIFO level display */
27 #define CSI_OFIFOL 0x14 /* CSI transmit FIFO level display */
28 #define CSI_IFIFO 0x18 /* CSI receive window */
29 #define CSI_OFIFO 0x1C /* CSI transmit window */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Drenesas,rzv2m-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 - $ref: spi-controller.yaml#
18 const: renesas,rzv2m-csi
28 - description: The clock used to generate the output clock (CSICLK)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dallwinner,sun4i-a10-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 CMOS Sensor Interface (CSI)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
13 description: |-
20 - const: allwinner,sun4i-a10-csi1
21 - const: allwinner,sun7i-a20-csi0
[all …]
Dallwinner,sun6i-a31-csi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 CMOS Sensor Interface (CSI)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
[all …]
Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
[all …]
Drenesas,vin.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
25 - items:
26 - enum:
[all …]
Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
Dstarfive,jh7110-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
15 consists of a VIN controller (Video In Controller, a top-level control unit)
20 const: starfive,jh7110-camss
25 reg-names:
27 - const: syscon
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drockchip-inno-csi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-csidphy.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/phy/phy-mipi-dphy.h>
60 /* Configure the count time of the THS-SETTLE by protocol. */
71 * The higher 16-bit of this register is used for write protection
93 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
134 struct clk *pclk; member
145 const struct dphy_drv_data *drv_data = priv->drv_data; in write_grf_reg()
146 const struct dphy_reg *reg = &drv_data->grf_regs[index]; in write_grf_reg()
148 if (reg->offset) in write_grf_reg()
149 regmap_write(priv->grf, reg->offset, in write_grf_reg()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/allwinner/
Dsun50i-a64-amarula-relic.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
7 #include "sun50i-a64.dtsi"
8 #include "sun50i-a64-cpu-opp.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Amarula A64-Relic";
14 compatible = "amarula,a64-relic", "allwinner,sun50i-a64";
21 stdout-path = "serial0:115200n8";
25 compatible = "i2c-gpio";
26 sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>;
[all …]
Dsun50i-a64-pinetab.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "sun50i-a64.dtsi"
10 #include "sun50i-a64-cpu-opp.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pwm/pwm.h>
18 compatible = "pine64,pinetab", "allwinner,sun50i-a64";
19 chassis-type = "tablet";
27 compatible = "pwm-backlight";
[all …]
/linux-6.12.1/drivers/pmdomain/imx/
Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
93 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
95 pm_runtime_put_noidle(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
[all …]
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun8i-s3-pinecube.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
6 /dts-v1/;
7 #include "sun8i-v3.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc5v0";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a09g011.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a09g011-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dovti,ov5640.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steve Longerbeam <slongerbeam@gmail.com>
13 - $ref: /schemas/media/video-interface-devices.yaml#
25 clock-names:
28 AVDD-supply:
31 DVDD-supply:
34 DOVDD-supply:
37 powerdown-gpios:
[all …]
Dti,ds90ub960.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
[all …]
/linux-6.12.1/drivers/pinctrl/sunxi/
Dpinctrl-suniv-f1c100s.c2 * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
12 * Copyright (C) 2014 Chen-Yu Tsai
14 * Chen-Yu Tsai <wens@csie.org>
18 * Maxime Ripard <maxime.ripard@free-electrons.com>
30 #include "pinctrl-sunxi.h"
256 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
264 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
272 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
279 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
287 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
[all …]
Dpinctrl-sun8i-v3s.c6 * Based on pinctrl-sun8i-h3.c, which is:
9 * Based on pinctrl-sun8i-a23.c, which is:
10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
23 #include "pinctrl-sunxi.h"
302 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
307 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
312 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
317 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
322 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
[all …]
Dpinctrl-sun8i-a33.c6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
267 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
271 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
275 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
279 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
283 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
287 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
[all …]
Dpinctrl-sun8i-h3.c6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
309 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
314 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
319 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
324 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
329 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
334 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
/linux-6.12.1/drivers/clk/
Dclk-stm32h7.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32h7-clks.h>
139 /* Micro-controller output clock parent */
178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable()
183 } while (bit_status && --timeout); in ready_gate_clk_enable()
201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable()
206 } while (bit_status && --timeout); in ready_gate_clk_disable()
227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate()
235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate()
[all …]

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