1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/phy/phy-mipi-dphy.h>
60 /* Configure the count time of the THS-SETTLE by protocol. */
71  * The higher 16-bit of this register is used for write protection
93 	{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
134 	struct clk *pclk;  member
145 	const struct dphy_drv_data *drv_data = priv->drv_data;  in write_grf_reg()
146 	const struct dphy_reg *reg = &drv_data->grf_regs[index];  in write_grf_reg()
148 	if (reg->offset)  in write_grf_reg()
149 		regmap_write(priv->grf, reg->offset,  in write_grf_reg()
150 			     HIWORD_UPDATE(value, reg->mask, reg->shift));  in write_grf_reg()
179 	const struct dphy_drv_data *drv_data = priv->drv_data;  in rockchip_inno_csidphy_ths_settle()
182 	val = readl(priv->phy_base + drv_data->ths_settle_offset + offset);  in rockchip_inno_csidphy_ths_settle()
185 	writel(val, priv->phy_base + drv_data->ths_settle_offset + offset);  in rockchip_inno_csidphy_ths_settle()
192 	const struct dphy_drv_data *drv_data = priv->drv_data;  in rockchip_inno_csidphy_configure()
193 	struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;  in rockchip_inno_csidphy_configure()
204 	data_rate_mbps = HZ_TO_MHZ(config->hs_clk_rate);  in rockchip_inno_csidphy_configure()
206 	dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",  in rockchip_inno_csidphy_configure()
207 		config->lanes, data_rate_mbps);  in rockchip_inno_csidphy_configure()
208 	for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {  in rockchip_inno_csidphy_configure()
209 		if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {  in rockchip_inno_csidphy_configure()
210 			hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;  in rockchip_inno_csidphy_configure()
215 		return -EINVAL;  in rockchip_inno_csidphy_configure()
217 	priv->hsfreq = hsfreq;  in rockchip_inno_csidphy_configure()
218 	priv->config = *config;  in rockchip_inno_csidphy_configure()
225 	const struct dphy_drv_data *drv_data = priv->drv_data;  in rockchip_inno_csidphy_power_on()
226 	u64 data_rate_mbps = HZ_TO_MHZ(priv->config.hs_clk_rate);  in rockchip_inno_csidphy_power_on()
230 	ret = clk_enable(priv->pclk);  in rockchip_inno_csidphy_power_on()
234 	ret = pm_runtime_resume_and_get(priv->dev);  in rockchip_inno_csidphy_power_on()
236 		clk_disable(priv->pclk);  in rockchip_inno_csidphy_power_on()
241 	if (drv_data->pwrctl_offset >= 0)  in rockchip_inno_csidphy_power_on()
244 		       priv->phy_base + drv_data->pwrctl_offset);  in rockchip_inno_csidphy_power_on()
247 	val = FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_MASK, GENMASK(priv->config.lanes - 1, 0)) |  in rockchip_inno_csidphy_power_on()
250 	writel(val, priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);  in rockchip_inno_csidphy_power_on()
253 	if (drv_data->pwrctl_offset >= 0)  in rockchip_inno_csidphy_power_on()
255 		       priv->phy_base + drv_data->pwrctl_offset);  in rockchip_inno_csidphy_power_on()
260 	       priv->phy_base + CSIDPHY_CTRL_DIG_RST);  in rockchip_inno_csidphy_power_on()
262 	       priv->phy_base + CSIDPHY_CTRL_DIG_RST);  in rockchip_inno_csidphy_power_on()
268 	if (data_rate_mbps > 1500 && drv_data->calib_offset >= 0) {  in rockchip_inno_csidphy_power_on()
270 		       priv->phy_base + drv_data->calib_offset +  in rockchip_inno_csidphy_power_on()
272 		for (i = 0; i < priv->config.lanes; i++)  in rockchip_inno_csidphy_power_on()
274 			       priv->phy_base + drv_data->calib_offset +  in rockchip_inno_csidphy_power_on()
278 	rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,  in rockchip_inno_csidphy_power_on()
280 	for (i = 0; i < priv->config.lanes; i++)  in rockchip_inno_csidphy_power_on()
281 		rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,  in rockchip_inno_csidphy_power_on()
286 		      GENMASK(priv->config.lanes - 1, 0));  in rockchip_inno_csidphy_power_on()
294 	const struct dphy_drv_data *drv_data = priv->drv_data;  in rockchip_inno_csidphy_power_off()
298 	       priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);  in rockchip_inno_csidphy_power_off()
301 	if (drv_data->pwrctl_offset >= 0)  in rockchip_inno_csidphy_power_off()
305 		       priv->phy_base + drv_data->pwrctl_offset);  in rockchip_inno_csidphy_power_off()
308 	pm_runtime_put(priv->dev);  in rockchip_inno_csidphy_power_off()
309 	clk_disable(priv->pclk);  in rockchip_inno_csidphy_power_off()
318 	return clk_prepare(priv->pclk);  in rockchip_inno_csidphy_init()
325 	clk_unprepare(priv->pclk);  in rockchip_inno_csidphy_exit()
340 	.pwrctl_offset = -1,
351 	.calib_offset = -1,
360 	.calib_offset = -1,
367 	.pwrctl_offset = -1,
377 		.compatible = "rockchip,px30-csi-dphy",
381 		.compatible = "rockchip,rk1808-csi-dphy",
385 		.compatible = "rockchip,rk3326-csi-dphy",
389 		.compatible = "rockchip,rk3368-csi-dphy",
393 		.compatible = "rockchip,rk3568-csi-dphy",
403 	struct device *dev = &pdev->dev;  in rockchip_inno_csidphy_probe()
409 		return -ENOMEM;  in rockchip_inno_csidphy_probe()
411 	priv->dev = dev;  in rockchip_inno_csidphy_probe()
414 	priv->drv_data = of_device_get_match_data(dev);  in rockchip_inno_csidphy_probe()
415 	if (!priv->drv_data) {  in rockchip_inno_csidphy_probe()
417 		return -ENODEV;  in rockchip_inno_csidphy_probe()
420 	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,  in rockchip_inno_csidphy_probe()
422 	if (IS_ERR(priv->grf)) {  in rockchip_inno_csidphy_probe()
424 		return PTR_ERR(priv->grf);  in rockchip_inno_csidphy_probe()
427 	priv->phy_base = devm_platform_ioremap_resource(pdev, 0);  in rockchip_inno_csidphy_probe()
428 	if (IS_ERR(priv->phy_base))  in rockchip_inno_csidphy_probe()
429 		return PTR_ERR(priv->phy_base);  in rockchip_inno_csidphy_probe()
431 	priv->pclk = devm_clk_get(dev, "pclk");  in rockchip_inno_csidphy_probe()
432 	if (IS_ERR(priv->pclk)) {  in rockchip_inno_csidphy_probe()
433 		dev_err(dev, "failed to get pclk\n");  in rockchip_inno_csidphy_probe()
434 		return PTR_ERR(priv->pclk);  in rockchip_inno_csidphy_probe()
437 	priv->rst = devm_reset_control_get(dev, "apb");  in rockchip_inno_csidphy_probe()
438 	if (IS_ERR(priv->rst)) {  in rockchip_inno_csidphy_probe()
440 		return PTR_ERR(priv->rst);  in rockchip_inno_csidphy_probe()
466 	pm_runtime_disable(priv->dev);  in rockchip_inno_csidphy_remove()
471 		.name = "rockchip-inno-csidphy",
479 MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
480 MODULE_DESCRIPTION("Rockchip MIPI Innosilicon CSI-DPHY driver");