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12

/linux-6.12.1/drivers/bus/
Darm-cci.c2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CCI Cache Coherent Interconnect
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
18 clusters, through memory mapped interface, with a global control register
19 space and multiple sets of interface control registers, one per slave
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Dcci-control-port.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CCI Interconnect Bus Masters
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
25 - |
27 #address-cells = <1>;
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/linux-6.12.1/arch/arm/boot/dts/samsung/
Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
[all …]
Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
[all …]
Dexynos5260.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 cpu-map {
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/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dqcom,i2c-cci.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
10 - Loic Poulain <loic.poulain@linaro.org>
11 - Robert Foss <robert.foss@linaro.org>
16 - enum:
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
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/linux-6.12.1/arch/arm/mach-versatile/
Dplatsmp-vexpress.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * The best way to detect a multi-cluster configuration in vexpress_smp_init_ops()
28 * is to detect if the kernel can take over CCI ports in vexpress_smp_init_ops()
29 * control. Loop over possible CPUs and check if CCI in vexpress_smp_init_ops()
30 * port control is available. in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
57 { .compatible = "arm,cortex-a5-scu", },
58 { .compatible = "arm,cortex-a9-scu", },
72 * system-wide flags register. The boot monitor waits in vexpress_smp_dt_prepare_cpus()
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
20 interrupt-parent = <&sysirq>;
[all …]
Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
[all …]
/linux-6.12.1/drivers/ata/
Dahci_ceva.c1 // SPDX-License-Identifier: GPL-2.0-only
37 /* Register bit definitions for cache control */
64 /* Port Control Register Bit Definitions */
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
82 /* Port Phy2Cfg Register */
87 /* Axi Cache Control Register */
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
135 /* TPSS TPRS scalars, CISE and Port Addr */ in ahci_ceva_setup()
[all …]
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
[all …]
/linux-6.12.1/drivers/usb/typec/ucsi/
Ducsi_ccg.c1 // SPDX-License-Identifier: GPL-2.0
3 * UCSI driver for Cypress CCGx Type-C controller
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
26 FW1, /* FW partition-1 (contains secondary fw) */
27 FW2, /* FW partition-2 (contains primary fw) */
197 __le32 cci; member
231 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
240 struct i2c_client *client = uc->client; in ccg_read()
241 const struct i2c_adapter_quirks *quirks = client->adapter->quirks; in ccg_read()
245 .addr = client->addr, in ccg_read()
[all …]
Ducsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 /* -------------------------------------------------------------------------- */
48 /* Command Status and Connector Change Indication (CCI) bits */
60 * struct ucsi_operations - UCSI I/O operations
62 * @read_cci: Read CCI register
64 * @sync_control: Blocking control operation
65 * @async_control: Non-blocking control operation
76 int (*read_cci)(struct ucsi *ucsi, u32 *cci);
95 /* -------------------------------------------------------------------------- */
193 /* -------------------------------------------------------------------------- */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dovti,ov5647.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
11 - Jacopo Mondi <jacopo@jmondi.org>
13 description: |-
14 The OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data
15 interfaces and CCI (I2C compatible) control bus.
29 pwdn-gpios:
33 port:
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Dgalaxycore,gc08a3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: GalaxyCore gc08a3 1/4" 8M Pixel MIPI CSI-2 sensor
11 - Zhi Mao <zhi.mao@mediatek.com>
14 The gc08a3 is a raw image sensor with an MIPI CSI-2 image data
15 interface and CCI (I2C compatible) control bus. The output format
28 dovdd-supply: true
30 avdd-supply: true
32 dvdd-supply: true
[all …]
Dgalaxycore,gc05a2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: GalaxyCore gc05a2 1/5" 5M Pixel MIPI CSI-2 sensor
11 - Zhi Mao <zhi.mao@mediatek.com>
14 The gc05a2 is a raw image sensor with an MIPI CSI-2 image data
15 interface and CCI (I2C compatible) control bus. The output format
28 dovdd-supply: true
30 avdd-supply: true
32 dvdd-supply: true
[all …]
Dsamsung,s5k6a3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data
14 interfaces and CCI (I2C compatible) control bus.
26 clock-names:
28 - const: extclk
30 clock-frequency:
38 afvdd-supply:
[all …]
Dhynix,hi846.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SK Hynix Hi-846 1/4" 8M Pixel MIPI CSI-2 sensor
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 The Hi-846 is a raw image sensor with an MIPI CSI-2 image data
14 interface and CCI (I2C compatible) control bus. The output format
18 - $ref: /schemas/media/video-interface-devices.yaml#
29 - description: Reference to the mclk clock.
[all …]
/linux-6.12.1/drivers/perf/
Darm-cci.c1 // SPDX-License-Identifier: GPL-2.0
2 // CCI Cache Coherent Interconnect PMU driver
3 // Copyright (C) 2013-2018 Arm Ltd.
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
35 #define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size)
37 #define CCI_PMU_CNTR_MASK ((1ULL << 32) - 1)
38 #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
41 ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
77 * @fixed_hw_cntrs - Number of fixed event counters
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
/linux-6.12.1/Documentation/driver-api/cxl/
Dmaturity-map.rst1 .. SPDX-License-Identifier: GPL-2.0
9 <https://computeexpresslink.org/cxl-specification-landing-page>`_ that
14 <https://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3ARe>`_,
20 the change-history of this document provides an overview summary of the
25 - [3] Mature: Work in this area is complete and no changes on the horizon.
29 - [2] Stabilizing: Major functionality operational, common cases are
32 - [1] Initial: Capability that has exited the Proof of Concept phase, but
36 - [0] Known gap: Feature is on a medium to long term horizon to
39 the linux-cxl@vger.kernel.org community has started to look at it.
41 - X: Out of scope for kernel enabling, or kernel enabling not required
[all …]

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