dts/samsung/exynos5422-cpus.dtsi

1 // SPDX-License-Identifier: GPL-2.0
13  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16  * from the LITTLE: Cortex-A7.
21 		#address-cells = <1>;
22 		#size-cells = <0>;
24 		cpu-map {
58 			compatible = "arm,cortex-a7";
61 			clock-frequency = <1000000000>;
62 			cci-control-port = <&cci_control0>;
63 			operating-points-v2 = <&cluster_a7_opp_table>;
64 			#cooling-cells = <2>; /* min followed by max */
65 			capacity-dmips-mhz = <539>;
66 			dynamic-power-coefficient = <90>;
71 			compatible = "arm,cortex-a7";
74 			clock-frequency = <1000000000>;
75 			cci-control-port = <&cci_control0>;
76 			operating-points-v2 = <&cluster_a7_opp_table>;
77 			#cooling-cells = <2>; /* min followed by max */
78 			capacity-dmips-mhz = <539>;
79 			dynamic-power-coefficient = <90>;
84 			compatible = "arm,cortex-a7";
87 			clock-frequency = <1000000000>;
88 			cci-control-port = <&cci_control0>;
89 			operating-points-v2 = <&cluster_a7_opp_table>;
90 			#cooling-cells = <2>; /* min followed by max */
91 			capacity-dmips-mhz = <539>;
92 			dynamic-power-coefficient = <90>;
97 			compatible = "arm,cortex-a7";
100 			clock-frequency = <1000000000>;
101 			cci-control-port = <&cci_control0>;
102 			operating-points-v2 = <&cluster_a7_opp_table>;
103 			#cooling-cells = <2>; /* min followed by max */
104 			capacity-dmips-mhz = <539>;
105 			dynamic-power-coefficient = <90>;
110 			compatible = "arm,cortex-a15";
113 			clock-frequency = <1800000000>;
114 			cci-control-port = <&cci_control1>;
115 			operating-points-v2 = <&cluster_a15_opp_table>;
116 			#cooling-cells = <2>; /* min followed by max */
117 			capacity-dmips-mhz = <1024>;
118 			dynamic-power-coefficient = <310>;
123 			compatible = "arm,cortex-a15";
126 			clock-frequency = <1800000000>;
127 			cci-control-port = <&cci_control1>;
128 			operating-points-v2 = <&cluster_a15_opp_table>;
129 			#cooling-cells = <2>; /* min followed by max */
130 			capacity-dmips-mhz = <1024>;
131 			dynamic-power-coefficient = <310>;
136 			compatible = "arm,cortex-a15";
139 			clock-frequency = <1800000000>;
140 			cci-control-port = <&cci_control1>;
141 			operating-points-v2 = <&cluster_a15_opp_table>;
142 			#cooling-cells = <2>; /* min followed by max */
143 			capacity-dmips-mhz = <1024>;
144 			dynamic-power-coefficient = <310>;
149 			compatible = "arm,cortex-a15";
152 			clock-frequency = <1800000000>;
153 			cci-control-port = <&cci_control1>;
154 			operating-points-v2 = <&cluster_a15_opp_table>;
155 			#cooling-cells = <2>; /* min followed by max */
156 			capacity-dmips-mhz = <1024>;
157 			dynamic-power-coefficient = <310>;
163 	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
168 	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;