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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Daspeed,ast2400-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/aspeed,ast2400-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed GPIO controller
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-gpio
16 - aspeed,ast2500-gpio
17 - aspeed,ast2600-gpio
26 gpio-controller: true
[all …]
Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
13 This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
15 AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
16 GPIO pins can be programmed to support the following options
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/fsi/
Dfsi-master-ast-cf.txt1 Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
2 ------------------------------------------------------------------------
5 - compatible =
6 "aspeed,ast2400-cf-fsi-master" for an AST2400 based system
8 "aspeed,ast2500-cf-fsi-master" for an AST2500 based system
10 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
11 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
12 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
13 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
14 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
[all …]
/linux-6.12.1/arch/arm/boot/dts/aspeed/
Daspeed-g4.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
39 compatible = "arm,arm926ej-s";
51 compatible = "simple-bus";
[all …]
Daspeed-bmc-opp-palmetto.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
26 no-map;
[all …]
Daspeed-bmc-microsoft-olympus.dts1 //SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "aspeed-g4.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "microsoft,olympus-bmc", "aspeed,ast2400";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
[all …]
Daspeed-bmc-opp-vesnin.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "aspeed-g4.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "yadro,vesnin-bmc", "aspeed,ast2400";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
[all …]
Daspeed-bmc-delta-ahe50dc.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "regulator-output"; \
10 vout-supply = <&efuse##n>; \
19 shunt-resistor-micro-ohms = <675>; \
22 regulator-name = __stringify(efuse##num##-reg); \
28 model = "Delta Power AHE-50DC";
29 compatible = "delta,ahe50dc-bmc", "aspeed,ast2400";
[all …]
Daspeed-bmc-quanta-q71l.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "aspeed-g4.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "quanta,q71l-bmc", "aspeed,ast2400";
30 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
44 no-map;
[all …]
Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
[all …]
/linux-6.12.1/drivers/net/mdio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 loadable module or built-in.
58 tristate "APM X-Gene SoC MDIO bus controller"
62 APM X-Gene SoC's.
72 third revision of the ASPEED MDIO register interface - the first two
73 revisions are the "old" and "new" interfaces found in the AST2400 and
75 continues to drive the embedded MDIO controller for the AST2400 and
109 tristate "GPIO lib-based bitbanged MDIO buses"
113 Supports GPIO lib-based MDIO busses.
116 will be called mdio-gpio.
[all …]
/linux-6.12.1/drivers/fsi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 FSI - the FRU Support Interface - is a simple bus for low-level
12 access to POWER-based hardware.
29 symlinks in /dev/fsi/by-path when this option is enabled.
32 tristate "GPIO-based FSI master"
36 This option enables a FSI master driver using GPIO lines.
52 This option enables a FSI master using the AST2400 and AST2500 GPIO
84 a pipe-like FSI device for communicating with the self boot engine
91 This option enables an SBEFIFO based On-Chip Controller (OCC) device
Dcf-fsi-fw.h1 /* SPDX-License-Identifier: GPL-2.0+ */
43 #define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
45 #define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
46 #define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
47 #define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
48 #define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
49 #define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
50 #define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
61 * +---------------------------+
64 * +---------------------------+
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Dfsi-master-ast-cf.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/gpio/consumer.h>
20 #include <linux/gpio/aspeed.h>
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
132 msg->msg <<= bits; in msg_push_bits()
133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()
134 msg->bits += bits; in msg_push_bits()
142 top = msg->bits & 0x3; in msg_push_crc()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/serial/
D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
71 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
72 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/driver.h>
49 * Note: The "value" register returns the input value when the GPIO is
52 * The "rdata" register returns the output value when the GPIO is
104 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() argument
110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
112 return gpio->base + bank->rdata_reg; in bank_reg()
114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
118 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
[all …]
Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
50 * represents disabled debouncing for the GPIO. Any other value for an element
85 * line even when the GPIO is configured as an output. Since
210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() argument
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
218 return gpio->base + bank->rdata_reg; in bank_reg()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # GPIO infrastructure and drivers
7 bool "GPIO Support"
9 This enables GPIO support through the generic GPIO library.
11 one or more of the GPIO drivers below.
47 this symbol, but new drivers should use the generic gpio-regmap
51 bool "Debug GPIO calls"
54 Say Y here to add some extra checks and diagnostics to GPIO calls.
57 non-sleeping contexts. They can make bitbanged serial protocols
62 bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
[all …]
/linux-6.12.1/drivers/pinctrl/aspeed/
Dpinctrl-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include "pinctrl-aspeed.h"
18 return pdata->pinmux.ngroups; in aspeed_pinctrl_get_groups_count()
26 return pdata->pinmux.groups[group].name; in aspeed_pinctrl_get_group_name()
35 *pins = &pdata->pinmux.groups[group].pins[0]; in aspeed_pinctrl_get_group_pins()
36 *npins = pdata->pinmux.groups[group].npins; in aspeed_pinctrl_get_group_pins()
44 seq_printf(s, " %s", dev_name(pctldev->dev)); in aspeed_pinctrl_pin_dbg_show()
51 return pdata->pinmux.nfunctions; in aspeed_pinmux_get_fn_count()
59 return pdata->pinmux.functions[function].name; in aspeed_pinmux_get_fn_name()
69 *groups = pdata->pinmux.functions[function].groups; in aspeed_pinmux_get_fn_groups()
[all …]
Dpinmux-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
26 * Here are some sample mux configurations from the AST2400 and AST2500
30 * D6 is a pin with a single function (beside GPIO); a high priority signal
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38 * C5 is a multi-signal pin (high and low priority signals). Here we touch
[all …]
Dpinctrl-aspeed-g4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/pinctrl/pinconf-generic.h>
20 #include "../pinctrl-utils.h"
21 #include "pinmux-aspeed.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
42 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
44 #define SCU80 0x80 /* Multi-function Pin Control #1 */
45 #define SCU84 0x84 /* Multi-function Pin Control #2 */
[all …]
/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
127 in the Aspeed AST2600, AST2500 and AST2400 SoCs when attached
155 supports spi-mem interface.
231 With a few GPIO pins, your system can bitbang the SPI protocol.
[all …]
/linux-6.12.1/drivers/hwmon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 sensors-detect script from the lm_sensors package. Read
21 <file:Documentation/hwmon/userspace-tools.rst> for details.
76 with SMpro co-processor.
278 will be called as370-hwmon.
311 will be called axi-fan-control
320 lm-sensors 2.10.1 for proper userspace support.
359 Only Intel-based Apple's computers are supported (MacBook Pro,
366 the laptop to act as a pinball machine-esque joystick.
381 will be called scmi-hwmon.
[all …]
Daspeed-pwm-tacho.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/consumer.h>
11 #include <linux/hwmon-sysfs.h>
47 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
74 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
87 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
97 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
105 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
112 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
116 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
[all …]

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