1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2400";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		i2c7 = &i2c7;
20		i2c8 = &i2c8;
21		i2c9 = &i2c9;
22		i2c10 = &i2c10;
23		i2c11 = &i2c11;
24		i2c12 = &i2c12;
25		i2c13 = &i2c13;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		serial3 = &uart4;
30		serial4 = &uart5;
31		serial5 = &vuart;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			compatible = "arm,arm926ej-s";
40			device_type = "cpu";
41			reg = <0>;
42		};
43	};
44
45	memory@40000000 {
46		device_type = "memory";
47		reg = <0x40000000 0>;
48	};
49
50	ahb {
51		compatible = "simple-bus";
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges;
55
56		fmc: spi@1e620000 {
57			reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
58			#address-cells = <1>;
59			#size-cells = <0>;
60			compatible = "aspeed,ast2400-fmc";
61			clocks = <&syscon ASPEED_CLK_AHB>;
62			status = "disabled";
63			interrupts = <19>;
64			flash@0 {
65				reg = < 0 >;
66				compatible = "jedec,spi-nor";
67				spi-rx-bus-width = <2>;
68				spi-max-frequency = <50000000>;
69				status = "disabled";
70			};
71			flash@1 {
72				reg = < 1 >;
73				compatible = "jedec,spi-nor";
74				spi-rx-bus-width = <2>;
75				spi-max-frequency = <50000000>;
76				status = "disabled";
77			};
78			flash@2 {
79				reg = < 2 >;
80				compatible = "jedec,spi-nor";
81				spi-rx-bus-width = <2>;
82				spi-max-frequency = <50000000>;
83				status = "disabled";
84			};
85			flash@3 {
86				reg = < 3 >;
87				compatible = "jedec,spi-nor";
88				spi-rx-bus-width = <2>;
89				spi-max-frequency = <50000000>;
90				status = "disabled";
91			};
92			flash@4 {
93				reg = < 4 >;
94				compatible = "jedec,spi-nor";
95				spi-rx-bus-width = <2>;
96				spi-max-frequency = <50000000>;
97				status = "disabled";
98			};
99		};
100
101		spi: spi@1e630000 {
102			reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
103			#address-cells = <1>;
104			#size-cells = <0>;
105			compatible = "aspeed,ast2400-spi";
106			clocks = <&syscon ASPEED_CLK_AHB>;
107			status = "disabled";
108			flash@0 {
109				reg = < 0 >;
110				compatible = "jedec,spi-nor";
111				spi-max-frequency = <50000000>;
112				spi-rx-bus-width = <2>;
113				status = "disabled";
114			};
115		};
116
117		vic: interrupt-controller@1e6c0080 {
118			compatible = "aspeed,ast2400-vic";
119			interrupt-controller;
120			#interrupt-cells = <1>;
121			valid-sources = <0xffffffff 0x0007ffff>;
122			reg = <0x1e6c0080 0x80>;
123		};
124
125		cvic: interrupt-controller@1e6c2000 {
126			compatible = "aspeed,ast2400-cvic", "aspeed,cvic";
127			valid-sources = <0x7fffffff>;
128			reg = <0x1e6c2000 0x80>;
129		};
130
131		mac0: ethernet@1e660000 {
132			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
133			reg = <0x1e660000 0x180>;
134			interrupts = <2>;
135			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
136			status = "disabled";
137		};
138
139		mac1: ethernet@1e680000 {
140			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
141			reg = <0x1e680000 0x180>;
142			interrupts = <3>;
143			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
144			status = "disabled";
145		};
146
147		ehci0: usb@1e6a1000 {
148			compatible = "aspeed,ast2400-ehci", "generic-ehci";
149			reg = <0x1e6a1000 0x100>;
150			interrupts = <5>;
151			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
152			pinctrl-names = "default";
153			pinctrl-0 = <&pinctrl_usb2h_default>;
154			status = "disabled";
155		};
156
157		uhci: usb@1e6b0000 {
158			compatible = "aspeed,ast2400-uhci", "generic-uhci";
159			reg = <0x1e6b0000 0x100>;
160			interrupts = <14>;
161			#ports = <3>;
162			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
163			status = "disabled";
164			/*
165			 * No default pinmux, it will follow EHCI, use an explicit pinmux
166			 * override if you don't enable EHCI
167			 */
168		};
169
170		vhub: usb-vhub@1e6a0000 {
171			compatible = "aspeed,ast2400-usb-vhub";
172			reg = <0x1e6a0000 0x300>;
173			interrupts = <5>;
174			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
175			aspeed,vhub-downstream-ports = <5>;
176			aspeed,vhub-generic-endpoints = <15>;
177			pinctrl-names = "default";
178			pinctrl-0 = <&pinctrl_usb2d_default>;
179			status = "disabled";
180		};
181
182		apb {
183			compatible = "simple-bus";
184			#address-cells = <1>;
185			#size-cells = <1>;
186			ranges;
187
188			syscon: syscon@1e6e2000 {
189				compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
190				reg = <0x1e6e2000 0x1a8>;
191				#address-cells = <1>;
192				#size-cells = <1>;
193				ranges = <0 0x1e6e2000 0x1000>;
194				#clock-cells = <1>;
195				#reset-cells = <1>;
196
197				p2a: p2a-control@2c {
198					reg = <0x2c 0x4>;
199					compatible = "aspeed,ast2400-p2a-ctrl";
200					status = "disabled";
201				};
202
203				silicon-id@7c {
204					compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";
205					reg = <0x7c 0x4>;
206				};
207
208				pinctrl: pinctrl@80 {
209					reg = <0x80 0x18>, <0xa0 0x10>;
210					compatible = "aspeed,ast2400-pinctrl";
211				};
212			};
213
214			rng: hwrng@1e6e2078 {
215				compatible = "timeriomem_rng";
216				reg = <0x1e6e2078 0x4>;
217				period = <1>;
218				quality = <100>;
219			};
220
221			adc: adc@1e6e9000 {
222				compatible = "aspeed,ast2400-adc";
223				reg = <0x1e6e9000 0xb0>;
224				clocks = <&syscon ASPEED_CLK_APB>;
225				resets = <&syscon ASPEED_RESET_ADC>;
226				#io-channel-cells = <1>;
227				status = "disabled";
228			};
229
230			sram: sram@1e720000 {
231				compatible = "mmio-sram";
232				reg = <0x1e720000 0x8000>;	// 32K
233				ranges;
234				#address-cells = <1>;
235				#size-cells = <1>;
236			};
237
238			video: video@1e700000 {
239				compatible = "aspeed,ast2400-video-engine";
240				reg = <0x1e700000 0x1000>;
241				clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
242					 <&syscon ASPEED_CLK_GATE_ECLK>;
243				clock-names = "vclk", "eclk";
244				interrupts = <7>;
245				status = "disabled";
246			};
247
248			sdmmc: sd-controller@1e740000 {
249				compatible = "aspeed,ast2400-sd-controller";
250				reg = <0x1e740000 0x100>;
251				#address-cells = <1>;
252				#size-cells = <1>;
253				ranges = <0 0x1e740000 0x10000>;
254				clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
255				status = "disabled";
256
257				sdhci0: sdhci@100 {
258					compatible = "aspeed,ast2400-sdhci";
259					reg = <0x100 0x100>;
260					interrupts = <26>;
261					sdhci,auto-cmd12;
262					clocks = <&syscon ASPEED_CLK_SDIO>;
263					status = "disabled";
264				};
265
266				sdhci1: sdhci@200 {
267					compatible = "aspeed,ast2400-sdhci";
268					reg = <0x200 0x100>;
269					interrupts = <26>;
270					sdhci,auto-cmd12;
271					clocks = <&syscon ASPEED_CLK_SDIO>;
272					status = "disabled";
273				};
274			};
275
276			gpio: gpio@1e780000 {
277				#gpio-cells = <2>;
278				gpio-controller;
279				compatible = "aspeed,ast2400-gpio";
280				reg = <0x1e780000 0x1000>;
281				interrupts = <20>;
282				gpio-ranges = <&pinctrl 0 0 220>;
283				clocks = <&syscon ASPEED_CLK_APB>;
284				interrupt-controller;
285				#interrupt-cells = <2>;
286			};
287
288			timer: timer@1e782000 {
289				/* This timer is a Faraday FTTMR010 derivative */
290				compatible = "aspeed,ast2400-timer";
291				reg = <0x1e782000 0x90>;
292				interrupts = <16 17 18 35 36 37 38 39>;
293				clocks = <&syscon ASPEED_CLK_APB>;
294				clock-names = "PCLK";
295			};
296
297			rtc: rtc@1e781000 {
298				compatible = "aspeed,ast2400-rtc";
299				reg = <0x1e781000 0x18>;
300				status = "disabled";
301			};
302
303			uart1: serial@1e783000 {
304				compatible = "ns16550a";
305				reg = <0x1e783000 0x20>;
306				reg-shift = <2>;
307				interrupts = <9>;
308				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
309				resets = <&lpc_reset 4>;
310				no-loopback-test;
311				status = "disabled";
312			};
313
314			uart5: serial@1e784000 {
315				compatible = "ns16550a";
316				reg = <0x1e784000 0x20>;
317				reg-shift = <2>;
318				interrupts = <10>;
319				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
320				no-loopback-test;
321				status = "disabled";
322			};
323
324			wdt1: watchdog@1e785000 {
325				compatible = "aspeed,ast2400-wdt";
326				reg = <0x1e785000 0x1c>;
327				clocks = <&syscon ASPEED_CLK_APB>;
328			};
329
330			wdt2: watchdog@1e785020 {
331				compatible = "aspeed,ast2400-wdt";
332				reg = <0x1e785020 0x1c>;
333				clocks = <&syscon ASPEED_CLK_APB>;
334			};
335
336			pwm_tacho: pwm-tacho-controller@1e786000 {
337				compatible = "aspeed,ast2400-pwm-tacho";
338				#address-cells = <1>;
339				#size-cells = <0>;
340				reg = <0x1e786000 0x1000>;
341				clocks = <&syscon ASPEED_CLK_24M>;
342				resets = <&syscon ASPEED_RESET_PWM>;
343				status = "disabled";
344			};
345
346			vuart: serial@1e787000 {
347				compatible = "aspeed,ast2400-vuart";
348				reg = <0x1e787000 0x40>;
349				reg-shift = <2>;
350				interrupts = <8>;
351				clocks = <&syscon ASPEED_CLK_APB>;
352				no-loopback-test;
353				status = "disabled";
354			};
355
356			lpc: lpc@1e789000 {
357				compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon";
358				reg = <0x1e789000 0x1000>;
359				reg-io-width = <4>;
360
361				#address-cells = <1>;
362				#size-cells = <1>;
363				ranges = <0x0 0x1e789000 0x1000>;
364
365				lpc_ctrl: lpc-ctrl@80 {
366					compatible = "aspeed,ast2400-lpc-ctrl";
367					reg = <0x80 0x10>;
368					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
369					status = "disabled";
370				};
371
372				lpc_snoop: lpc-snoop@90 {
373					compatible = "aspeed,ast2400-lpc-snoop";
374					reg = <0x90 0x8>;
375					interrupts = <8>;
376					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
377					status = "disabled";
378				};
379
380				lhc: lhc@a0 {
381					compatible = "aspeed,ast2400-lhc";
382					reg = <0xa0 0x24 0xc8 0x8>;
383				};
384
385				lpc_reset: reset-controller@98 {
386					compatible = "aspeed,ast2400-lpc-reset";
387					reg = <0x98 0x4>;
388					#reset-cells = <1>;
389				};
390
391				ibt: ibt@140 {
392					compatible = "aspeed,ast2400-ibt-bmc";
393					reg = <0x140 0x18>;
394					interrupts = <8>;
395					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
396					status = "disabled";
397				};
398
399				uart_routing: uart-routing@9c {
400					compatible = "aspeed,ast2400-uart-routing";
401					reg = <0x9c 0x4>;
402					status = "disabled";
403				};
404			};
405
406			peci0: peci-controller@1e78b000 {
407				compatible = "aspeed,ast2400-peci";
408				reg = <0x1e78b000 0x60>;
409				interrupts = <15>;
410				clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
411				resets = <&syscon ASPEED_RESET_PECI>;
412				cmd-timeout-ms = <1000>;
413				clock-frequency = <1000000>;
414				status = "disabled";
415			};
416
417			uart2: serial@1e78d000 {
418				compatible = "ns16550a";
419				reg = <0x1e78d000 0x20>;
420				reg-shift = <2>;
421				interrupts = <32>;
422				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
423				resets = <&lpc_reset 5>;
424				no-loopback-test;
425				status = "disabled";
426			};
427
428			uart3: serial@1e78e000 {
429				compatible = "ns16550a";
430				reg = <0x1e78e000 0x20>;
431				reg-shift = <2>;
432				interrupts = <33>;
433				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
434				resets = <&lpc_reset 6>;
435				no-loopback-test;
436				status = "disabled";
437			};
438
439			uart4: serial@1e78f000 {
440				compatible = "ns16550a";
441				reg = <0x1e78f000 0x20>;
442				reg-shift = <2>;
443				interrupts = <34>;
444				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
445				resets = <&lpc_reset 7>;
446				no-loopback-test;
447				status = "disabled";
448			};
449
450			i2c: bus@1e78a000 {
451				compatible = "simple-bus";
452				#address-cells = <1>;
453				#size-cells = <1>;
454				ranges = <0 0x1e78a000 0x1000>;
455			};
456		};
457	};
458};
459
460&i2c {
461	i2c_ic: interrupt-controller@0 {
462		#interrupt-cells = <1>;
463		compatible = "aspeed,ast2400-i2c-ic";
464		reg = <0x0 0x40>;
465		interrupts = <12>;
466		interrupt-controller;
467	};
468
469	i2c0: i2c@40 {
470		#address-cells = <1>;
471		#size-cells = <0>;
472
473		reg = <0x40 0x40>;
474		compatible = "aspeed,ast2400-i2c-bus";
475		clocks = <&syscon ASPEED_CLK_APB>;
476		resets = <&syscon ASPEED_RESET_I2C>;
477		bus-frequency = <100000>;
478		interrupts = <0>;
479		interrupt-parent = <&i2c_ic>;
480		status = "disabled";
481		/* Does not need pinctrl properties */
482	};
483
484	i2c1: i2c@80 {
485		#address-cells = <1>;
486		#size-cells = <0>;
487
488		reg = <0x80 0x40>;
489		compatible = "aspeed,ast2400-i2c-bus";
490		clocks = <&syscon ASPEED_CLK_APB>;
491		resets = <&syscon ASPEED_RESET_I2C>;
492		bus-frequency = <100000>;
493		interrupts = <1>;
494		interrupt-parent = <&i2c_ic>;
495		status = "disabled";
496		/* Does not need pinctrl properties */
497	};
498
499	i2c2: i2c@c0 {
500		#address-cells = <1>;
501		#size-cells = <0>;
502
503		reg = <0xc0 0x40>;
504		compatible = "aspeed,ast2400-i2c-bus";
505		clocks = <&syscon ASPEED_CLK_APB>;
506		resets = <&syscon ASPEED_RESET_I2C>;
507		bus-frequency = <100000>;
508		interrupts = <2>;
509		interrupt-parent = <&i2c_ic>;
510		pinctrl-names = "default";
511		pinctrl-0 = <&pinctrl_i2c3_default>;
512		status = "disabled";
513	};
514
515	i2c3: i2c@100 {
516		#address-cells = <1>;
517		#size-cells = <0>;
518
519		reg = <0x100 0x40>;
520		compatible = "aspeed,ast2400-i2c-bus";
521		clocks = <&syscon ASPEED_CLK_APB>;
522		resets = <&syscon ASPEED_RESET_I2C>;
523		bus-frequency = <100000>;
524		interrupts = <3>;
525		interrupt-parent = <&i2c_ic>;
526		pinctrl-names = "default";
527		pinctrl-0 = <&pinctrl_i2c4_default>;
528		status = "disabled";
529	};
530
531	i2c4: i2c@140 {
532		#address-cells = <1>;
533		#size-cells = <0>;
534
535		reg = <0x140 0x40>;
536		compatible = "aspeed,ast2400-i2c-bus";
537		clocks = <&syscon ASPEED_CLK_APB>;
538		resets = <&syscon ASPEED_RESET_I2C>;
539		bus-frequency = <100000>;
540		interrupts = <4>;
541		interrupt-parent = <&i2c_ic>;
542		pinctrl-names = "default";
543		pinctrl-0 = <&pinctrl_i2c5_default>;
544		status = "disabled";
545	};
546
547	i2c5: i2c@180 {
548		#address-cells = <1>;
549		#size-cells = <0>;
550
551		reg = <0x180 0x40>;
552		compatible = "aspeed,ast2400-i2c-bus";
553		clocks = <&syscon ASPEED_CLK_APB>;
554		resets = <&syscon ASPEED_RESET_I2C>;
555		bus-frequency = <100000>;
556		interrupts = <5>;
557		interrupt-parent = <&i2c_ic>;
558		pinctrl-names = "default";
559		pinctrl-0 = <&pinctrl_i2c6_default>;
560		status = "disabled";
561	};
562
563	i2c6: i2c@1c0 {
564		#address-cells = <1>;
565		#size-cells = <0>;
566
567		reg = <0x1c0 0x40>;
568		compatible = "aspeed,ast2400-i2c-bus";
569		clocks = <&syscon ASPEED_CLK_APB>;
570		resets = <&syscon ASPEED_RESET_I2C>;
571		bus-frequency = <100000>;
572		interrupts = <6>;
573		interrupt-parent = <&i2c_ic>;
574		pinctrl-names = "default";
575		pinctrl-0 = <&pinctrl_i2c7_default>;
576		status = "disabled";
577	};
578
579	i2c7: i2c@300 {
580		#address-cells = <1>;
581		#size-cells = <0>;
582
583		reg = <0x300 0x40>;
584		compatible = "aspeed,ast2400-i2c-bus";
585		clocks = <&syscon ASPEED_CLK_APB>;
586		resets = <&syscon ASPEED_RESET_I2C>;
587		bus-frequency = <100000>;
588		interrupts = <7>;
589		interrupt-parent = <&i2c_ic>;
590		pinctrl-names = "default";
591		pinctrl-0 = <&pinctrl_i2c8_default>;
592		status = "disabled";
593	};
594
595	i2c8: i2c@340 {
596		#address-cells = <1>;
597		#size-cells = <0>;
598
599		reg = <0x340 0x40>;
600		compatible = "aspeed,ast2400-i2c-bus";
601		clocks = <&syscon ASPEED_CLK_APB>;
602		resets = <&syscon ASPEED_RESET_I2C>;
603		bus-frequency = <100000>;
604		interrupts = <8>;
605		interrupt-parent = <&i2c_ic>;
606		pinctrl-names = "default";
607		pinctrl-0 = <&pinctrl_i2c9_default>;
608		status = "disabled";
609	};
610
611	i2c9: i2c@380 {
612		#address-cells = <1>;
613		#size-cells = <0>;
614
615		reg = <0x380 0x40>;
616		compatible = "aspeed,ast2400-i2c-bus";
617		clocks = <&syscon ASPEED_CLK_APB>;
618		resets = <&syscon ASPEED_RESET_I2C>;
619		bus-frequency = <100000>;
620		interrupts = <9>;
621		interrupt-parent = <&i2c_ic>;
622		pinctrl-names = "default";
623		pinctrl-0 = <&pinctrl_i2c10_default>;
624		status = "disabled";
625	};
626
627	i2c10: i2c@3c0 {
628		#address-cells = <1>;
629		#size-cells = <0>;
630
631		reg = <0x3c0 0x40>;
632		compatible = "aspeed,ast2400-i2c-bus";
633		clocks = <&syscon ASPEED_CLK_APB>;
634		resets = <&syscon ASPEED_RESET_I2C>;
635		bus-frequency = <100000>;
636		interrupts = <10>;
637		interrupt-parent = <&i2c_ic>;
638		pinctrl-names = "default";
639		pinctrl-0 = <&pinctrl_i2c11_default>;
640		status = "disabled";
641	};
642
643	i2c11: i2c@400 {
644		#address-cells = <1>;
645		#size-cells = <0>;
646
647		reg = <0x400 0x40>;
648		compatible = "aspeed,ast2400-i2c-bus";
649		clocks = <&syscon ASPEED_CLK_APB>;
650		resets = <&syscon ASPEED_RESET_I2C>;
651		bus-frequency = <100000>;
652		interrupts = <11>;
653		interrupt-parent = <&i2c_ic>;
654		pinctrl-names = "default";
655		pinctrl-0 = <&pinctrl_i2c12_default>;
656		status = "disabled";
657	};
658
659	i2c12: i2c@440 {
660		#address-cells = <1>;
661		#size-cells = <0>;
662
663		reg = <0x440 0x40>;
664		compatible = "aspeed,ast2400-i2c-bus";
665		clocks = <&syscon ASPEED_CLK_APB>;
666		resets = <&syscon ASPEED_RESET_I2C>;
667		bus-frequency = <100000>;
668		interrupts = <12>;
669		interrupt-parent = <&i2c_ic>;
670		pinctrl-names = "default";
671		pinctrl-0 = <&pinctrl_i2c13_default>;
672		status = "disabled";
673	};
674
675	i2c13: i2c@480 {
676		#address-cells = <1>;
677		#size-cells = <0>;
678
679		reg = <0x480 0x40>;
680		compatible = "aspeed,ast2400-i2c-bus";
681		clocks = <&syscon ASPEED_CLK_APB>;
682		resets = <&syscon ASPEED_RESET_I2C>;
683		bus-frequency = <100000>;
684		interrupts = <13>;
685		interrupt-parent = <&i2c_ic>;
686		pinctrl-names = "default";
687		pinctrl-0 = <&pinctrl_i2c14_default>;
688		status = "disabled";
689	};
690};
691
692&pinctrl {
693	pinctrl_acpi_default: acpi_default {
694		function = "ACPI";
695		groups = "ACPI";
696	};
697
698	pinctrl_adc0_default: adc0_default {
699		function = "ADC0";
700		groups = "ADC0";
701	};
702
703	pinctrl_adc1_default: adc1_default {
704		function = "ADC1";
705		groups = "ADC1";
706	};
707
708	pinctrl_adc10_default: adc10_default {
709		function = "ADC10";
710		groups = "ADC10";
711	};
712
713	pinctrl_adc11_default: adc11_default {
714		function = "ADC11";
715		groups = "ADC11";
716	};
717
718	pinctrl_adc12_default: adc12_default {
719		function = "ADC12";
720		groups = "ADC12";
721	};
722
723	pinctrl_adc13_default: adc13_default {
724		function = "ADC13";
725		groups = "ADC13";
726	};
727
728	pinctrl_adc14_default: adc14_default {
729		function = "ADC14";
730		groups = "ADC14";
731	};
732
733	pinctrl_adc15_default: adc15_default {
734		function = "ADC15";
735		groups = "ADC15";
736	};
737
738	pinctrl_adc2_default: adc2_default {
739		function = "ADC2";
740		groups = "ADC2";
741	};
742
743	pinctrl_adc3_default: adc3_default {
744		function = "ADC3";
745		groups = "ADC3";
746	};
747
748	pinctrl_adc4_default: adc4_default {
749		function = "ADC4";
750		groups = "ADC4";
751	};
752
753	pinctrl_adc5_default: adc5_default {
754		function = "ADC5";
755		groups = "ADC5";
756	};
757
758	pinctrl_adc6_default: adc6_default {
759		function = "ADC6";
760		groups = "ADC6";
761	};
762
763	pinctrl_adc7_default: adc7_default {
764		function = "ADC7";
765		groups = "ADC7";
766	};
767
768	pinctrl_adc8_default: adc8_default {
769		function = "ADC8";
770		groups = "ADC8";
771	};
772
773	pinctrl_adc9_default: adc9_default {
774		function = "ADC9";
775		groups = "ADC9";
776	};
777
778	pinctrl_bmcint_default: bmcint_default {
779		function = "BMCINT";
780		groups = "BMCINT";
781	};
782
783	pinctrl_ddcclk_default: ddcclk_default {
784		function = "DDCCLK";
785		groups = "DDCCLK";
786	};
787
788	pinctrl_ddcdat_default: ddcdat_default {
789		function = "DDCDAT";
790		groups = "DDCDAT";
791	};
792
793	pinctrl_extrst_default: extrst_default {
794		function = "EXTRST";
795		groups = "EXTRST";
796	};
797
798	pinctrl_flack_default: flack_default {
799		function = "FLACK";
800		groups = "FLACK";
801	};
802
803	pinctrl_flbusy_default: flbusy_default {
804		function = "FLBUSY";
805		groups = "FLBUSY";
806	};
807
808	pinctrl_flwp_default: flwp_default {
809		function = "FLWP";
810		groups = "FLWP";
811	};
812
813	pinctrl_gpid_default: gpid_default {
814		function = "GPID";
815		groups = "GPID";
816	};
817
818	pinctrl_gpid0_default: gpid0_default {
819		function = "GPID0";
820		groups = "GPID0";
821	};
822
823	pinctrl_gpid2_default: gpid2_default {
824		function = "GPID2";
825		groups = "GPID2";
826	};
827
828	pinctrl_gpid4_default: gpid4_default {
829		function = "GPID4";
830		groups = "GPID4";
831	};
832
833	pinctrl_gpid6_default: gpid6_default {
834		function = "GPID6";
835		groups = "GPID6";
836	};
837
838	pinctrl_gpie0_default: gpie0_default {
839		function = "GPIE0";
840		groups = "GPIE0";
841	};
842
843	pinctrl_gpie2_default: gpie2_default {
844		function = "GPIE2";
845		groups = "GPIE2";
846	};
847
848	pinctrl_gpie4_default: gpie4_default {
849		function = "GPIE4";
850		groups = "GPIE4";
851	};
852
853	pinctrl_gpie6_default: gpie6_default {
854		function = "GPIE6";
855		groups = "GPIE6";
856	};
857
858	pinctrl_i2c10_default: i2c10_default {
859		function = "I2C10";
860		groups = "I2C10";
861	};
862
863	pinctrl_i2c11_default: i2c11_default {
864		function = "I2C11";
865		groups = "I2C11";
866	};
867
868	pinctrl_i2c12_default: i2c12_default {
869		function = "I2C12";
870		groups = "I2C12";
871	};
872
873	pinctrl_i2c13_default: i2c13_default {
874		function = "I2C13";
875		groups = "I2C13";
876	};
877
878	pinctrl_i2c14_default: i2c14_default {
879		function = "I2C14";
880		groups = "I2C14";
881	};
882
883	pinctrl_i2c3_default: i2c3_default {
884		function = "I2C3";
885		groups = "I2C3";
886	};
887
888	pinctrl_i2c4_default: i2c4_default {
889		function = "I2C4";
890		groups = "I2C4";
891	};
892
893	pinctrl_i2c5_default: i2c5_default {
894		function = "I2C5";
895		groups = "I2C5";
896	};
897
898	pinctrl_i2c6_default: i2c6_default {
899		function = "I2C6";
900		groups = "I2C6";
901	};
902
903	pinctrl_i2c7_default: i2c7_default {
904		function = "I2C7";
905		groups = "I2C7";
906	};
907
908	pinctrl_i2c8_default: i2c8_default {
909		function = "I2C8";
910		groups = "I2C8";
911	};
912
913	pinctrl_i2c9_default: i2c9_default {
914		function = "I2C9";
915		groups = "I2C9";
916	};
917
918	pinctrl_lpcpd_default: lpcpd_default {
919		function = "LPCPD";
920		groups = "LPCPD";
921	};
922
923	pinctrl_lpcpme_default: lpcpme_default {
924		function = "LPCPME";
925		groups = "LPCPME";
926	};
927
928	pinctrl_lpcrst_default: lpcrst_default {
929		function = "LPCRST";
930		groups = "LPCRST";
931	};
932
933	pinctrl_lpcsmi_default: lpcsmi_default {
934		function = "LPCSMI";
935		groups = "LPCSMI";
936	};
937
938	pinctrl_mac1link_default: mac1link_default {
939		function = "MAC1LINK";
940		groups = "MAC1LINK";
941	};
942
943	pinctrl_mac2link_default: mac2link_default {
944		function = "MAC2LINK";
945		groups = "MAC2LINK";
946	};
947
948	pinctrl_mdio1_default: mdio1_default {
949		function = "MDIO1";
950		groups = "MDIO1";
951	};
952
953	pinctrl_mdio2_default: mdio2_default {
954		function = "MDIO2";
955		groups = "MDIO2";
956	};
957
958	pinctrl_ncts1_default: ncts1_default {
959		function = "NCTS1";
960		groups = "NCTS1";
961	};
962
963	pinctrl_ncts2_default: ncts2_default {
964		function = "NCTS2";
965		groups = "NCTS2";
966	};
967
968	pinctrl_ncts3_default: ncts3_default {
969		function = "NCTS3";
970		groups = "NCTS3";
971	};
972
973	pinctrl_ncts4_default: ncts4_default {
974		function = "NCTS4";
975		groups = "NCTS4";
976	};
977
978	pinctrl_ndcd1_default: ndcd1_default {
979		function = "NDCD1";
980		groups = "NDCD1";
981	};
982
983	pinctrl_ndcd2_default: ndcd2_default {
984		function = "NDCD2";
985		groups = "NDCD2";
986	};
987
988	pinctrl_ndcd3_default: ndcd3_default {
989		function = "NDCD3";
990		groups = "NDCD3";
991	};
992
993	pinctrl_ndcd4_default: ndcd4_default {
994		function = "NDCD4";
995		groups = "NDCD4";
996	};
997
998	pinctrl_ndsr1_default: ndsr1_default {
999		function = "NDSR1";
1000		groups = "NDSR1";
1001	};
1002
1003	pinctrl_ndsr2_default: ndsr2_default {
1004		function = "NDSR2";
1005		groups = "NDSR2";
1006	};
1007
1008	pinctrl_ndsr3_default: ndsr3_default {
1009		function = "NDSR3";
1010		groups = "NDSR3";
1011	};
1012
1013	pinctrl_ndsr4_default: ndsr4_default {
1014		function = "NDSR4";
1015		groups = "NDSR4";
1016	};
1017
1018	pinctrl_ndtr1_default: ndtr1_default {
1019		function = "NDTR1";
1020		groups = "NDTR1";
1021	};
1022
1023	pinctrl_ndtr2_default: ndtr2_default {
1024		function = "NDTR2";
1025		groups = "NDTR2";
1026	};
1027
1028	pinctrl_ndtr3_default: ndtr3_default {
1029		function = "NDTR3";
1030		groups = "NDTR3";
1031	};
1032
1033	pinctrl_ndtr4_default: ndtr4_default {
1034		function = "NDTR4";
1035		groups = "NDTR4";
1036	};
1037
1038	pinctrl_ndts4_default: ndts4_default {
1039		function = "NDTS4";
1040		groups = "NDTS4";
1041	};
1042
1043	pinctrl_nri1_default: nri1_default {
1044		function = "NRI1";
1045		groups = "NRI1";
1046	};
1047
1048	pinctrl_nri2_default: nri2_default {
1049		function = "NRI2";
1050		groups = "NRI2";
1051	};
1052
1053	pinctrl_nri3_default: nri3_default {
1054		function = "NRI3";
1055		groups = "NRI3";
1056	};
1057
1058	pinctrl_nri4_default: nri4_default {
1059		function = "NRI4";
1060		groups = "NRI4";
1061	};
1062
1063	pinctrl_nrts1_default: nrts1_default {
1064		function = "NRTS1";
1065		groups = "NRTS1";
1066	};
1067
1068	pinctrl_nrts2_default: nrts2_default {
1069		function = "NRTS2";
1070		groups = "NRTS2";
1071	};
1072
1073	pinctrl_nrts3_default: nrts3_default {
1074		function = "NRTS3";
1075		groups = "NRTS3";
1076	};
1077
1078	pinctrl_oscclk_default: oscclk_default {
1079		function = "OSCCLK";
1080		groups = "OSCCLK";
1081	};
1082
1083	pinctrl_pwm0_default: pwm0_default {
1084		function = "PWM0";
1085		groups = "PWM0";
1086	};
1087
1088	pinctrl_pwm1_default: pwm1_default {
1089		function = "PWM1";
1090		groups = "PWM1";
1091	};
1092
1093	pinctrl_pwm2_default: pwm2_default {
1094		function = "PWM2";
1095		groups = "PWM2";
1096	};
1097
1098	pinctrl_pwm3_default: pwm3_default {
1099		function = "PWM3";
1100		groups = "PWM3";
1101	};
1102
1103	pinctrl_pwm4_default: pwm4_default {
1104		function = "PWM4";
1105		groups = "PWM4";
1106	};
1107
1108	pinctrl_pwm5_default: pwm5_default {
1109		function = "PWM5";
1110		groups = "PWM5";
1111	};
1112
1113	pinctrl_pwm6_default: pwm6_default {
1114		function = "PWM6";
1115		groups = "PWM6";
1116	};
1117
1118	pinctrl_pwm7_default: pwm7_default {
1119		function = "PWM7";
1120		groups = "PWM7";
1121	};
1122
1123	pinctrl_rgmii1_default: rgmii1_default {
1124		function = "RGMII1";
1125		groups = "RGMII1";
1126	};
1127
1128	pinctrl_rgmii2_default: rgmii2_default {
1129		function = "RGMII2";
1130		groups = "RGMII2";
1131	};
1132
1133	pinctrl_rmii1_default: rmii1_default {
1134		function = "RMII1";
1135		groups = "RMII1";
1136	};
1137
1138	pinctrl_rmii2_default: rmii2_default {
1139		function = "RMII2";
1140		groups = "RMII2";
1141	};
1142
1143	pinctrl_rom16_default: rom16_default {
1144		function = "ROM16";
1145		groups = "ROM16";
1146	};
1147
1148	pinctrl_rom8_default: rom8_default {
1149		function = "ROM8";
1150		groups = "ROM8";
1151	};
1152
1153	pinctrl_romcs1_default: romcs1_default {
1154		function = "ROMCS1";
1155		groups = "ROMCS1";
1156	};
1157
1158	pinctrl_romcs2_default: romcs2_default {
1159		function = "ROMCS2";
1160		groups = "ROMCS2";
1161	};
1162
1163	pinctrl_romcs3_default: romcs3_default {
1164		function = "ROMCS3";
1165		groups = "ROMCS3";
1166	};
1167
1168	pinctrl_romcs4_default: romcs4_default {
1169		function = "ROMCS4";
1170		groups = "ROMCS4";
1171	};
1172
1173	pinctrl_rxd1_default: rxd1_default {
1174		function = "RXD1";
1175		groups = "RXD1";
1176	};
1177
1178	pinctrl_rxd2_default: rxd2_default {
1179		function = "RXD2";
1180		groups = "RXD2";
1181	};
1182
1183	pinctrl_rxd3_default: rxd3_default {
1184		function = "RXD3";
1185		groups = "RXD3";
1186	};
1187
1188	pinctrl_rxd4_default: rxd4_default {
1189		function = "RXD4";
1190		groups = "RXD4";
1191	};
1192
1193	pinctrl_salt1_default: salt1_default {
1194		function = "SALT1";
1195		groups = "SALT1";
1196	};
1197
1198	pinctrl_salt2_default: salt2_default {
1199		function = "SALT2";
1200		groups = "SALT2";
1201	};
1202
1203	pinctrl_salt3_default: salt3_default {
1204		function = "SALT3";
1205		groups = "SALT3";
1206	};
1207
1208	pinctrl_salt4_default: salt4_default {
1209		function = "SALT4";
1210		groups = "SALT4";
1211	};
1212
1213	pinctrl_sd1_default: sd1_default {
1214		function = "SD1";
1215		groups = "SD1";
1216	};
1217
1218	pinctrl_sd2_default: sd2_default {
1219		function = "SD2";
1220		groups = "SD2";
1221	};
1222
1223	pinctrl_sgpmck_default: sgpmck_default {
1224		function = "SGPMCK";
1225		groups = "SGPMCK";
1226	};
1227
1228	pinctrl_sgpmi_default: sgpmi_default {
1229		function = "SGPMI";
1230		groups = "SGPMI";
1231	};
1232
1233	pinctrl_sgpmld_default: sgpmld_default {
1234		function = "SGPMLD";
1235		groups = "SGPMLD";
1236	};
1237
1238	pinctrl_sgpmo_default: sgpmo_default {
1239		function = "SGPMO";
1240		groups = "SGPMO";
1241	};
1242
1243	pinctrl_sgpsck_default: sgpsck_default {
1244		function = "SGPSCK";
1245		groups = "SGPSCK";
1246	};
1247
1248	pinctrl_sgpsi0_default: sgpsi0_default {
1249		function = "SGPSI0";
1250		groups = "SGPSI0";
1251	};
1252
1253	pinctrl_sgpsi1_default: sgpsi1_default {
1254		function = "SGPSI1";
1255		groups = "SGPSI1";
1256	};
1257
1258	pinctrl_sgpsld_default: sgpsld_default {
1259		function = "SGPSLD";
1260		groups = "SGPSLD";
1261	};
1262
1263	pinctrl_sioonctrl_default: sioonctrl_default {
1264		function = "SIOONCTRL";
1265		groups = "SIOONCTRL";
1266	};
1267
1268	pinctrl_siopbi_default: siopbi_default {
1269		function = "SIOPBI";
1270		groups = "SIOPBI";
1271	};
1272
1273	pinctrl_siopbo_default: siopbo_default {
1274		function = "SIOPBO";
1275		groups = "SIOPBO";
1276	};
1277
1278	pinctrl_siopwreq_default: siopwreq_default {
1279		function = "SIOPWREQ";
1280		groups = "SIOPWREQ";
1281	};
1282
1283	pinctrl_siopwrgd_default: siopwrgd_default {
1284		function = "SIOPWRGD";
1285		groups = "SIOPWRGD";
1286	};
1287
1288	pinctrl_sios3_default: sios3_default {
1289		function = "SIOS3";
1290		groups = "SIOS3";
1291	};
1292
1293	pinctrl_sios5_default: sios5_default {
1294		function = "SIOS5";
1295		groups = "SIOS5";
1296	};
1297
1298	pinctrl_siosci_default: siosci_default {
1299		function = "SIOSCI";
1300		groups = "SIOSCI";
1301	};
1302
1303	pinctrl_spi1_default: spi1_default {
1304		function = "SPI1";
1305		groups = "SPI1";
1306	};
1307
1308	pinctrl_spi1debug_default: spi1debug_default {
1309		function = "SPI1DEBUG";
1310		groups = "SPI1DEBUG";
1311	};
1312
1313	pinctrl_spi1passthru_default: spi1passthru_default {
1314		function = "SPI1PASSTHRU";
1315		groups = "SPI1PASSTHRU";
1316	};
1317
1318	pinctrl_spics1_default: spics1_default {
1319		function = "SPICS1";
1320		groups = "SPICS1";
1321	};
1322
1323	pinctrl_timer3_default: timer3_default {
1324		function = "TIMER3";
1325		groups = "TIMER3";
1326	};
1327
1328	pinctrl_timer4_default: timer4_default {
1329		function = "TIMER4";
1330		groups = "TIMER4";
1331	};
1332
1333	pinctrl_timer5_default: timer5_default {
1334		function = "TIMER5";
1335		groups = "TIMER5";
1336	};
1337
1338	pinctrl_timer6_default: timer6_default {
1339		function = "TIMER6";
1340		groups = "TIMER6";
1341	};
1342
1343	pinctrl_timer7_default: timer7_default {
1344		function = "TIMER7";
1345		groups = "TIMER7";
1346	};
1347
1348	pinctrl_timer8_default: timer8_default {
1349		function = "TIMER8";
1350		groups = "TIMER8";
1351	};
1352
1353	pinctrl_txd1_default: txd1_default {
1354		function = "TXD1";
1355		groups = "TXD1";
1356	};
1357
1358	pinctrl_txd2_default: txd2_default {
1359		function = "TXD2";
1360		groups = "TXD2";
1361	};
1362
1363	pinctrl_txd3_default: txd3_default {
1364		function = "TXD3";
1365		groups = "TXD3";
1366	};
1367
1368	pinctrl_txd4_default: txd4_default {
1369		function = "TXD4";
1370		groups = "TXD4";
1371	};
1372
1373	pinctrl_uart6_default: uart6_default {
1374		function = "UART6";
1375		groups = "UART6";
1376	};
1377
1378	pinctrl_usbcki_default: usbcki_default {
1379		function = "USBCKI";
1380		groups = "USBCKI";
1381	};
1382
1383	pinctrl_usb2h_default: usb2h_default {
1384		function = "USB2H1";
1385		groups = "USB2H1";
1386	};
1387
1388	pinctrl_usb2d_default: usb2d_default {
1389		function = "USB2D1";
1390		groups = "USB2D1";
1391	};
1392
1393	pinctrl_vgabios_rom_default: vgabios_rom_default {
1394		function = "VGABIOS_ROM";
1395		groups = "VGABIOS_ROM";
1396	};
1397
1398	pinctrl_vgahs_default: vgahs_default {
1399		function = "VGAHS";
1400		groups = "VGAHS";
1401	};
1402
1403	pinctrl_vgavs_default: vgavs_default {
1404		function = "VGAVS";
1405		groups = "VGAVS";
1406	};
1407
1408	pinctrl_vpi18_default: vpi18_default {
1409		function = "VPI18";
1410		groups = "VPI18";
1411	};
1412
1413	pinctrl_vpi24_default: vpi24_default {
1414		function = "VPI24";
1415		groups = "VPI24";
1416	};
1417
1418	pinctrl_vpi30_default: vpi30_default {
1419		function = "VPI30";
1420		groups = "VPI30";
1421	};
1422
1423	pinctrl_vpo12_default: vpo12_default {
1424		function = "VPO12";
1425		groups = "VPO12";
1426	};
1427
1428	pinctrl_vpo24_default: vpo24_default {
1429		function = "VPO24";
1430		groups = "VPO24";
1431	};
1432
1433	pinctrl_wdtrst1_default: wdtrst1_default {
1434		function = "WDTRST1";
1435		groups = "WDTRST1";
1436	};
1437
1438	pinctrl_wdtrst2_default: wdtrst2_default {
1439		function = "WDTRST2";
1440		groups = "WDTRST2";
1441	};
1442};
1443