Lines Matching +full:ast2400 +full:- +full:gpio

1 /* SPDX-License-Identifier: GPL-2.0+ */
43 #define	 FW_CONTROL_DUMMY_RD	0x00000004	/* Extra dummy read (AST2400) */
45 #define HDR_CLOCK_GPIO_VADDR	0x90	/* 2 bytes offset from GPIO base */
46 #define HDR_CLOCK_GPIO_DADDR	0x92	/* 2 bytes offset from GPIO base */
47 #define HDR_DATA_GPIO_VADDR	0x94	/* 2 bytes offset from GPIO base */
48 #define HDR_DATA_GPIO_DADDR	0x96	/* 2 bytes offset from GPIO base */
49 #define HDR_TRANS_GPIO_VADDR	0x98	/* 2 bytes offset from GPIO base */
50 #define HDR_TRANS_GPIO_DADDR	0x9a	/* 2 bytes offset from GPIO base */
61  * +---------------------------+
64  * +---------------------------+
118 #define	INT_CNT			0x30 /* 32-bit interrupt count */
119 #define	BAD_INT_VEC		0x34 /* 32-bit bad interrupt vector # */
120 #define	CF_STARTED		0x38 /* byte, set to -1 when copro started */
121 #define	CLK_CNT			0x3c /* 32-bit, clock count (debug only) */
124  *  SRAM layout: GPIO arbitration part