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/linux-6.12.1/drivers/clk/spear/
Dclk-vco-pll.c6 * VCO-PLL clock implementation
9 #define pr_fmt(fmt) "clk-vco-pll: " fmt
18 * DOC: VCO-PLL clock
20 * VCO and PLL rate are derived from following equations:
23 * vco = (2 * M[15:8] * Fin)/N
26 * vco = (2 * M[15:0] * Fin)/(256 * N)
30 * vco and pll are very closely bound to each other, "vco needs to program:
34 * clk_register_vco_pll() registers instances of both vco & pll.
36 * set_rate to vco. A single rate table exists for both the clocks, which
94 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { in clk_pll_round_rate_index()
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/linux-6.12.1/drivers/clk/versatile/
Dclk-icst.c3 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
37 * struct clk_icst - ICST VCO clock wrapper
40 * @vcoreg_off: VCO register address
41 * @lockreg_off: VCO lock register address
59 * vco_get() - get ICST VCO settings from a certain ICST
61 * @vco: the VCO struct to return the value in
63 static int vco_get(struct clk_icst *icst, struct icst_vco *vco) in vco_get() argument
81 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
82 vco->r = 22; in vco_get()
83 vco->s = 1; in vco_get()
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Dicst.c27 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) in icst_hz() argument
29 u64 dividend = p->ref * 2 * (u64)(vco.v + 8); in icst_hz()
30 u32 divisor = (vco.r + 2) * p->s2div[vco.s]; in icst_hz()
49 struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; in icst_hz_to_vco() local
66 return vco; in icst_hz_to_vco()
68 vco.s = p->idx2s[i]; in icst_hz_to_vco()
91 vco.v = vd - 8; in icst_hz_to_vco()
92 vco.r = rd - 2; in icst_hz_to_vco()
99 return vco; in icst_hz_to_vco()
Dclk-icst.h18 * struct clk_icst_desc - descriptor for the ICST VCO
20 * @vco_offset: offset to the ICST VCO from the provided memory base
21 * @lock_offset: offset to the ICST VCO locking register from the provided
Dicst.h30 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco);
34 * ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V).
44 * ICST525 VCO frequency must be between 10MHz and 200MHz (3V) or 320MHz (5V).
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cdclk.c87 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
89 * , where vco is the frequency generated by the PLL; cd2x_div
101 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
104 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
316 unsigned int vco; in intel_hpll_vco() local
336 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
337 if (vco == 0) in intel_hpll_vco()
338 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
341 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
343 return vco; in intel_hpll_vco()
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Dintel_dpll.c36 } dot, vco, n, m, m1, m2, p, p1; member
45 .vco = { .min = 908000, .max = 1512000 },
58 .vco = { .min = 908000, .max = 1512000 },
71 .vco = { .min = 908000, .max = 1512000 },
84 .vco = { .min = 1400000, .max = 2800000 },
97 .vco = { .min = 1400000, .max = 2800000 },
111 .vco = { .min = 1750000, .max = 3500000},
126 .vco = { .min = 1750000, .max = 3500000},
139 .vco = { .min = 1750000, .max = 3500000 },
153 .vco = { .min = 1750000, .max = 3500000 },
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/linux-6.12.1/drivers/clk/berlin/
Dberlin2-avpll.c19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
26 * Also, here and there the VCO registers are a bit different with
115 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_is_enabled() local
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
127 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_enable() local
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
131 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable()
135 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
142 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_disable() local
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/linux-6.12.1/drivers/clk/
Dclk-si544.c45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
203 u64 vco; in si544_calc_muldiv() local
228 vco = FVCO_MIN + ls_freq - 1; in si544_calc_muldiv()
229 do_div(vco, ls_freq); in si544_calc_muldiv()
230 settings->hs_div = vco; in si544_calc_muldiv()
237 /* Calculate VCO frequency (in 10..12GHz range) */ in si544_calc_muldiv()
238 vco = (u64)ls_freq * settings->hs_div; in si544_calc_muldiv()
241 tmp = do_div(vco, FXO); in si544_calc_muldiv()
242 settings->fb_div_int = vco; in si544_calc_muldiv()
245 vco = (u64)tmp << 32; in si544_calc_muldiv()
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Dclk-lmk04832.c242 * @vco: reference to the internal VCO clock
244 * @vco_rate: user provided VCO rate
261 struct clk_hw vco; member
330 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); in lmk04832_vco_is_enabled()
345 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); in lmk04832_vco_prepare()
363 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); in lmk04832_vco_unprepare()
377 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); in lmk04832_vco_recalc_rate()
413 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
416 * @rate: Desired output rate for the VCO
418 * The LMK04832 has 2 internal VCO, each with independent operating ranges.
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/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Dradio_2055.h72 #define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
73 #define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
74 #define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
75 #define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
76 #define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
77 #define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
78 #define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
79 #define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
80 #define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
81 #define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
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/linux-6.12.1/drivers/clk/pistachio/
Dclk-pll.c199 u64 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_frac_set_rate() local
209 /* calculate vco */ in pll_gf40lp_frac_set_rate()
210 vco = params->fref; in pll_gf40lp_frac_set_rate()
211 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
212 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
214 if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) in pll_gf40lp_frac_set_rate()
215 pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, in pll_gf40lp_frac_set_rate()
222 if (val > vco / 16) in pll_gf40lp_frac_set_rate()
224 name, val, vco / 16); in pll_gf40lp_frac_set_rate()
356 u32 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_laint_set_rate() local
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/linux-6.12.1/drivers/media/tuners/
Dfc0011.c21 FC11_REG_VCO, /* VCO */
22 FC11_REG_VCOSEL, /* VCO select */
30 FC11_REG_VCOCAL, /* VCO calibrate */
39 FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
40 FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
51 FC11_VCOCAL_RUN = 0, /* VCO calibration run */
52 FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
53 FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
54 FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
132 /* Initiate VCO calibration */
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/linux-6.12.1/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
167 /* Calc VCO at full accuracy */ in ProgramClock()
172 * Check it's within restricted VCO range in ProgramClock()
175 * against VCO limit in ProgramClock()
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/linux-6.12.1/drivers/clk/analogbits/
Dwrpll-cln28hpc.c47 /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
50 /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
136 * @vco_rate: pointer to a u64 to store the computed VCO rate into
141 * desired target VCO rate into the variable pointed to by @vco_rate.
230 u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; in wrpll_configure_for_rate() local
259 /* Calculate the Q shift and target VCO rate */ in wrpll_configure_for_rate()
284 vco = vco_pre * f; in wrpll_configure_for_rate()
287 if (vco > target_vco_rate) { in wrpll_configure_for_rate()
289 vco = vco_pre * f; in wrpll_configure_for_rate()
290 } else if (vco < MIN_VCO_FREQ) { in wrpll_configure_for_rate()
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dfsl,plldig.yaml30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
Darm,syscon-icst.yaml74 description: The VCO register
77 description: Parent clock for the ICST VCO
87 vco-offset:
89 description: Offset to the VCO register for the oscillator
105 vco-offset = <0x00>;
Dqcom,sm8450-dispcc.yaml35 - description: VCO DIV clock from DP PHY0
37 - description: VCO DIV clock from DP PHY1
39 - description: VCO DIV clock from DP PHY2
41 - description: VCO DIV clock from DP PHY3
Dqcom,dispcc-sc8280xp.yaml31 - description: DisplayPort 0 VCO div clock
33 - description: DisplayPort 1 VCO div clock
35 - description: DisplayPort 2 VCO div clock
37 - description: DisplayPort 3 VCO div clock
Dqcom,sm8550-dispcc.yaml40 - description: VCO DIV clock from DP PHY0
42 - description: VCO DIV clock from DP PHY1
44 - description: VCO DIV clock from DP PHY2
46 - description: VCO DIV clock from DP PHY3
Dqcom,dispcc-sm8x50.yaml38 - description: VCO DIV clock from DP PHY
40 - description: VCO DIV clock from eDP PHY
42 - description: VCO DIV clock from DP1 PHY
44 - description: VCO DIV clock from DP2 PHY
/linux-6.12.1/drivers/video/fbdev/matrox/
Dg450_pll.c106 unsigned int *vco, unsigned int fout) in g450_firstpll() argument
114 *vco = vcomax; in g450_firstpll()
116 *vco = fout; in g450_firstpll()
131 *vco = tvco; in g450_firstpll()
133 return g450_nextpll(minfo, pi, vco, 0xFF0000 | p); in g450_firstpll()
437 unsigned int vco; in __g450_setclk() local
440 vco = g450_mnp2vco(minfo, mnp); in __g450_setclk()
441 delta = pll_freq_delta(fout, g450_vco2f(mnp, vco)); in __g450_setclk()
444 sorted equally good frequencies from lower VCO in __g450_setclk()
448 /* all else being equal except VCO, in __g450_setclk()
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/linux-6.12.1/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_uw2453.c25 * fractional divide ratio) and 3 (VCO config).
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
30 * When this happens, we remember which VCO configuration produced the lock
34 * If we do not see a PLL lock on any standard VCO config, we fall back on an
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
58 /* This table stores the synthesizer fractional divide ratio for *all* VCO
78 /* Here is the data for all the standard VCO configurations. We shrink our
206 /* The VCO configuration for autocal (all channels) */
235 /* index into synth/VCO config tables where PLL lock was found
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/linux-6.12.1/drivers/clk/bcm/
Dclk-iproc-pll.c27 /* number of VCO frequency bands */
115 * Based on the target frequency, find a match from the VCO frequency parameter
277 struct iproc_pll_vco_param *vco) in pll_fractional_change_only() argument
293 if (ndiv_int != vco->ndiv_int) in pll_fractional_change_only()
299 if (pdiv != vco->pdiv) in pll_fractional_change_only()
305 static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco, in pll_set_rate() argument
311 unsigned long rate = vco->rate; in pll_set_rate()
321 if (vco->pdiv == 0) in pll_set_rate()
324 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
326 /* determine Ki and Kp index based on target VCO frequency */ in pll_set_rate()
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/linux-6.12.1/drivers/char/hw_random/
Dn2rng.h13 #define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
14 #define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
29 #define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */
30 #define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */

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