Lines Matching full:vco
87 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
89 * , where vco is the frequency generated by the PLL; cd2x_div
101 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
104 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
316 unsigned int vco; in intel_hpll_vco() local
336 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
337 if (vco == 0) in intel_hpll_vco()
338 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
341 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
343 return vco; in intel_hpll_vco()
358 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
367 switch (cdclk_config->vco) { in g33_get_cdclk()
384 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
390 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
391 cdclk_config->vco, tmp); in g33_get_cdclk()
440 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
449 switch (cdclk_config->vco) { in i965gm_get_cdclk()
463 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
469 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
470 cdclk_config->vco, tmp); in i965gm_get_cdclk()
481 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
487 switch (cdclk_config->vco) { in gm45_get_cdclk()
498 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
499 cdclk_config->vco, tmp); in gm45_get_cdclk()
570 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
573 cdclk_config->vco); in vlv_get_cdclk()
886 static int skl_calc_cdclk(int min_cdclk, int vco) in skl_calc_cdclk() argument
888 if (vco == 8640000) { in skl_calc_cdclk()
927 cdclk_config->vco = 0; in skl_dpll0_update()
950 cdclk_config->vco = 8100000; in skl_dpll0_update()
954 cdclk_config->vco = 8640000; in skl_dpll0_update()
971 if (cdclk_config->vco == 0) in skl_get_cdclk()
976 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
1029 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco) in skl_set_preferred_cdclk_vco() argument
1031 bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1033 i915->display.cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1039 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_link_rate() argument
1041 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1045 * taking into account the VCO required to operate the eDP panel at the in skl_dpll0_link_rate()
1046 * desired frequency. The usual DP link rates operate with a VCO of in skl_dpll0_link_rate()
1047 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. in skl_dpll0_link_rate()
1050 * works with vco. in skl_dpll0_link_rate()
1052 if (vco == 8640000) in skl_dpll0_link_rate()
1058 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
1065 skl_dpll0_link_rate(dev_priv, vco)); in skl_dpll0_enable()
1074 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1076 /* We'll want to keep using the current vco from now on. */ in skl_dpll0_enable()
1077 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1088 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1092 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1098 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1119 int vco = cdclk_config->vco; in skl_set_cdclk() local
1128 * use the corresponding VCO freq as that always leads to using the in skl_set_cdclk()
1132 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1144 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1146 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1147 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1152 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1164 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1165 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1202 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1225 dev_priv->display.cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1235 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1237 * Use the current vco as our initial in skl_cdclk_init_hw()
1238 * guess as to what the preferred vco is. in skl_cdclk_init_hw()
1242 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1248 cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1249 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1250 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1251 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1262 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1466 static int cdclk_divider(int cdclk, int vco, u16 waveform) in cdclk_divider() argument
1469 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), in cdclk_divider()
1622 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1625 cdclk_config->vco = 0; in bxt_de_pll_readout()
1638 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1657 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1693 cdclk_config->vco, size * div); in bxt_get_cdclk()
1695 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1718 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1721 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1723 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1735 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1747 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1750 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in icl_cdclk_pll_enable() argument
1752 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1765 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1768 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) in adlp_cdclk_pll_crawl() argument
1770 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1789 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1813 int cdclk, int vco, u16 waveform) in bxt_cdclk_cd2x_div_sel() argument
1815 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1816 switch (cdclk_divider(cdclk, vco, waveform)) { in bxt_cdclk_cd2x_div_sel()
1820 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1853 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) in icl_cdclk_pll_update() argument
1855 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1856 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1859 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1860 icl_cdclk_pll_enable(i915, vco); in icl_cdclk_pll_update()
1863 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) in bxt_cdclk_pll_update() argument
1865 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1866 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1869 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1870 bxt_de_pll_enable(i915, vco); in bxt_cdclk_pll_update()
1885 static bool cdclk_pll_is_unknown(unsigned int vco) in cdclk_pll_is_unknown() argument
1889 * case when the vco is set to ~0 in the in cdclk_pll_is_unknown()
1892 return vco == ~0; in cdclk_pll_is_unknown()
1912 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
1935 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) in cdclk_compute_crawl_and_squash_midpoint()
1946 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || in cdclk_compute_crawl_and_squash_midpoint()
1947 old_cdclk_config->vco == new_cdclk_config->vco || in cdclk_compute_crawl_and_squash_midpoint()
1952 old_cdclk_config->vco, old_waveform); in cdclk_compute_crawl_and_squash_midpoint()
1954 new_cdclk_config->vco, new_waveform); in cdclk_compute_crawl_and_squash_midpoint()
1970 * The mid cdclk config should have the new vco. in cdclk_compute_crawl_and_squash_midpoint()
1974 mid_cdclk_config->vco = old_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1978 mid_cdclk_config->vco = new_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1984 mid_cdclk_config->vco, in cdclk_compute_crawl_and_squash_midpoint()
2004 dev_priv->display.cdclk.hw.vco > 0; in pll_enable_wa_needed()
2012 int vco = cdclk_config->vco; in bxt_cdclk_ctl() local
2018 val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2042 int vco = cdclk_config->vco; in _bxt_set_cdclk() local
2044 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2045 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
2046 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
2047 adlp_cdclk_pll_crawl(dev_priv, vco); in _bxt_set_cdclk()
2053 icl_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
2055 bxt_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
2160 int cdclk, vco; in bxt_sanitize_cdclk() local
2165 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2174 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
2175 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
2176 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2206 dev_priv->display.cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2216 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2227 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2239 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
2285 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2287 if (a->vco == 0 || b->vco == 0) in intel_cdclk_can_crawl_and_squash()
2296 return a->vco != b->vco && in intel_cdclk_can_crawl_and_squash()
2310 * The vco and cd2x divider will change independently in intel_cdclk_can_crawl()
2313 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2314 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2316 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
2317 a->vco != b->vco && in intel_cdclk_can_crawl()
2336 a->vco != 0 && in intel_cdclk_can_squash()
2337 a->vco == b->vco && in intel_cdclk_can_squash()
2354 a->vco != b->vco || in intel_cdclk_clock_changed()
2387 a->vco != 0 && in intel_cdclk_can_cd2x_update()
2388 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
2411 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2412 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
3028 int vco, i; in skl_dpll0_vco() local
3030 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
3031 if (!vco) in skl_dpll0_vco()
3032 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3042 * DPLL0 VCO may need to be adjusted to get the correct in skl_dpll0_vco()
3048 vco = 8640000; in skl_dpll0_vco()
3051 vco = 8100000; in skl_dpll0_vco()
3056 return vco; in skl_dpll0_vco()
3063 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
3069 vco = skl_dpll0_vco(state); in skl_modeset_calc_cdclk()
3071 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
3073 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
3079 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
3081 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
3097 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
3108 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3110 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
3118 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3120 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
3419 int max_cdclk, vco; in intel_update_max_cdclk() local
3421 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3422 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3425 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
3427 * if the preferred vco is 8100 instead. in intel_update_max_cdclk()
3438 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()