36 	} dot, vco, n, m, m1, m2, p, p1;  member
45 	.vco = { .min = 908000, .max = 1512000 },
58 	.vco = { .min = 908000, .max = 1512000 },
71 	.vco = { .min = 908000, .max = 1512000 },
84 	.vco = { .min = 1400000, .max = 2800000 },
97 	.vco = { .min = 1400000, .max = 2800000 },
111 	.vco = { .min = 1750000, .max = 3500000},
126 	.vco = { .min = 1750000, .max = 3500000},
139 	.vco = { .min = 1750000, .max = 3500000 },
153 	.vco = { .min = 1750000, .max = 3500000 },
167 	.vco = { .min = 1700000, .max = 3500000 },
182 	.vco = { .min = 1700000, .max = 3500000 },
200 	.vco = { .min = 1760000, .max = 3510000 },
213 	.vco = { .min = 1760000, .max = 3510000 },
226 	.vco = { .min = 1760000, .max = 3510000 },
240 	.vco = { .min = 1760000, .max = 3510000 },
253 	.vco = { .min = 1760000, .max = 3510000 },
272 	.vco = { .min = 4000000, .max = 6000000 },
288 	.vco = { .min = 4800000, .max = 6480000 },
298 	.vco = { .min = 4800000, .max = 6700000 },
309  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
321 	clock->vco = clock->n == 0 ? 0 :  in pnv_calc_dpll_params()
324 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in pnv_calc_dpll_params()
339 	clock->vco = clock->n + 2 == 0 ? 0 :  in i9xx_calc_dpll_params()
342 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in i9xx_calc_dpll_params()
352 	clock->vco = clock->n == 0 ? 0 :  in vlv_calc_dpll_params()
355 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in vlv_calc_dpll_params()
365 	clock->vco = clock->n == 0 ? 0 :  in chv_calc_dpll_params()
368 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in chv_calc_dpll_params()
603 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)  in intel_pll_is_valid()
1118 	 *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock  in i8xx_dpll()
2084 	if (clock->vco == 5400000) {  in chv_prepare_pll()
2089 	} else if (clock->vco <= 6200000) {  in chv_prepare_pll()
2094 	} else if (clock->vco <= 6480000) {  in chv_prepare_pll()