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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
[all …]
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@foss.st.com>
27 - st,stm32mp1-fmc2-ebi
28 - st,stm32mp25-fmc2-ebi
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Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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/linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
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/linux-6.12.1/Documentation/devicetree/bindings/leds/
Dleds-lm36274.txt1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
4 The backlight boost provides the power to bias four parallel LED strings with
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
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/linux-6.12.1/arch/powerpc/platforms/85xx/
Dp1022_ds.c42 * Board-specific initialization of the DIU. This code should probably be
77 * Note that we need to byte-swap the value before it's written to the AD
133 * obtain the upper four bits, we need to scan the LAW table. The entry which
134 * maps to the localbus will contain the upper four bits.
140 * If we only have 32-bit addressing, then the BRx address *is* the in lbc_br_to_phys()
153 /* Extract the upper four bits */ in lbc_br_to_phys()
181 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); in p1022ds_set_monitor_port()
193 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc"); in p1022ds_set_monitor_port()
205 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law"); in p1022ds_set_monitor_port()
217 iprop = of_get_property(law_node, "fsl,num-laws", NULL); in p1022ds_set_monitor_port()
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/linux-6.12.1/drivers/thermal/mediatek/
Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
109 /* The number of sensing points per bank */
119 #define MT8173_TEMP_MIN -20000
198 /* The number of sensing points per bank */
219 /* The number of sensing points per bank */
258 /* The number of sensing points per bank */
276 /* The number of sensing points per bank */
472 * The MT8173 thermal controller has four banks. Each bank can read up to
473 * four temperature sensors simultaneously. The MT8173 has a total of 5
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/linux-6.12.1/drivers/gpio/
Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
14 * An optional second bank, with ports E, F, G, and H, may be present, starting
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
45 * @base: Base address of the register block for a GPIO bank
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
[all …]
Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 unsigned int bank; member
48 * The @timer_users has four elements but the first element is unused. This is
211 const struct aspeed_gpio_bank *bank, in bank_reg() argument
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
218 return gpio->base + bank->rdata_reg; in bank_reg()
220 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
[all …]
/linux-6.12.1/drivers/hwspinlock/
Domap_hwspinlock.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
10 * Suman Anna <s-anna@ti.com>
40 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_trylock()
48 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_unlock()
77 struct hwspinlock_device *bank; in omap_hwspinlock_probe() local
91 devm_pm_runtime_enable(&pdev->dev); in omap_hwspinlock_probe()
92 ret = pm_runtime_resume_and_get(&pdev->dev); in omap_hwspinlock_probe()
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap-zoom-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
13 * Four port TL16CP754C serial port on GPMC,
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
[all …]
Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
[all …]
Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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/linux-6.12.1/Documentation/admin-guide/perf/
Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
24 four groups:
[all …]
/linux-6.12.1/drivers/mtd/maps/
Dnetsc520.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* netsc520.c -- MTD map driver for AMD NetSc520 Demonstration Board
5 * based on sc520cdp.c by Sysgo Real-Time Solutions GmbH
8 * from AMD. It has a single back of 16 megs of 32-bit Flash ROM and another
23 ** The single, 16 megabyte flash bank is divided into four virtual
34 ** not be touched - it is possible to corrupt the BIOS image by
70 .name = "netsc520 Flash Bank",
89 return -EIO; in init_netsc520()
102 return -ENXIO; in init_netsc520()
105 mymtd->owner = THIS_MODULE; in init_netsc520()
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_gt_topology.c1 // SPDX-License-Identifier: MIT
23 if (drm_WARN_ON(&gt_to_xe(gt)->drm, numregs > XE_MAX_DSS_FUSE_REGS)) in load_dss_mask()
45 * Pre-Xe_HP platforms inverted the bit meaning (disable instead in load_eu_mask()
67 * gen_l3_mask_from_pattern - Replicate a bit pattern according to a mask
69 * It is used to compute the L3 bank masks in a generic format on
80 * ----------
94 * ----------
151 } else if (xe->info.platform == XE_PVC) { in load_l3_bank_mask()
162 } else if (xe->info.platform == XE_DG2) { in load_l3_bank_mask()
207 drm_WARN_ON(&xe->drm, num_geometry_regs > 3); in xe_gt_topology_init()
[all …]
/linux-6.12.1/Documentation/hwmon/
Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
40 internal state that allows no clean access (Bank with ID register is not
42 parameter; this will put it into a more well-behaved state first.
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
116 ----------------
118 - This driver is only for Winbond W83792D C version device, there
120 calculation method to in6-in7(measured value, limits) is a little
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Ddt2817.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
16 * A very simple digital I/O card. Four banks of 8 lines, each bank
24 * [0] - I/O port base base address
38 unsigned int chan = CR_CHAN(insn->chanspec); in dt2817_dio_insn_config()
56 if (s->io_bits & 0x000000ff) in dt2817_dio_insn_config()
58 if (s->io_bits & 0x0000ff00) in dt2817_dio_insn_config()
60 if (s->io_bits & 0x00ff0000) in dt2817_dio_insn_config()
62 if (s->io_bits & 0xff000000) in dt2817_dio_insn_config()
65 outb(oe, dev->iobase + DT2817_CR); in dt2817_dio_insn_config()
[all …]
/linux-6.12.1/include/sound/
Dopl3.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Definitions of the OPL-3 registers.
9 * Hannu Savolainen 1993-1996
11 * The OPL-3 mode is switched on by writing 0x01, to the offset 5
34 * register of the voice (0xC0-0xC8). In 4 OP voices these bits are
76 #define OPL3_COMPOSITE_SINE_WAVE_MODE 0x80 /* Don't use with OPL-3? */
91 * register number just add the operator offset to the bank offset
133 * F-Number low bits (0xA0 to 0xA8).
138 * F-number high bits / Key on / Block (octave) (0xB0 to 0xB8)
148 * These registers have two new bits when the OPL-3 mode
[all …]
/linux-6.12.1/arch/mips/include/asm/sgi/
Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
17 * board, which are grouped into four banks
21 /* HEART can support up to four CPUs */
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/regulator/
Dnxp,pf8x00-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/nxp,pf8x00-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Troy Kisky <troy.kisky@boundarydevices.com>
15 applications. It features seven high efficiency buck converters, four
16 linear and one vsnvs regulators. It has built-in one time programmable
17 fuse bank for device configurations.
22 - nxp,pf8100
[all …]

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