asm/sgi/heart.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7  *		 2007-2015 Joshua Kinard <kumba@gentoo.org>
17  * board, which are grouped into four banks
21 /* HEART can support up to four CPUs */
27  * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28  * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29  * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30  * @mem_refresh: HEART_MEM_REF - purpose unknown.
31  * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32  * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33  * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
34  * @fc_mode: HEART_FC_MODE - Purpose Unknown, possibly for GFX flow control.
35  * @fc_timer_limit: HEART_FC_TIMER_LIMIT - purpose unknown.
36  * @fc_addr: HEART_FC0_ADDR, HEART_FC1_ADDR - purpose unknown.
37  * @fc_credit_cnt: HEART_FC0_CR_CNT, HEART_FC1_CR_CNT - purpose unknown.
38  * @fc_timer: HEART_FC0_TIMER, HEART_FC1_TIMER - purpose unknown.
39  * @status: HEART_STATUS - HEART status information.
40  * @bus_err_addr: HEART_BERR_ADDR - likely contains addr of recent SIGBUS.
41  * @bus_err_misc: HEART_BERR_MISC - purpose unknown.
42  * @mem_err_addr: HEART_MEMERR_ADDR - likely contains addr of recent mem err.
43  * @mem_err_data: HEART_MEMERR_DATA - purpose unknown.
44  * @piur_acc_err: HEART_PIUR_ACC_ERR - likely for access err to HEART regs.
45  * @mlan_clock_div: HEART_MLAN_CLK_DIV - MicroLAN clock divider.
46  * @mlan_ctrl: HEART_MLAN_CTL - MicroLAN control.
47  * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49  * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
50  * @imr: HEART_IMR0 to HEART_IMR3 - per-cpu interrupt mask register.
51  * @set_isr: HEART_SET_ISR - set interrupt status register.
52  * @clear_isr: HEART_CLR_ISR - clear interrupt status register.
53  * @isr: HEART_ISR - interrupt status register (read-only).
54  * @imsr: HEART_IMSR - purpose unknown.
55  * @cause: HEART_CAUSE - HEART cause information.
56  * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
57  * @count: HEART_COUNT - 52-bit counter.
58  * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
59  * @compare: HEART_COMPARE - 24-bit compare.
60  * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
61  * @trigger: HEART_TRIGGER - purpose unknown.
62  * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
63  * @cpuid: HEART_PRID - contains CPU ID of CPU currently accessing HEART.
64  * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
65  * @sync: HEART_SYNC - purpose unknown.
72  * Implementation note: All HEART registers are 64bits-wide, but the mem_cfg
76  * per bank.  Each 32bit read accesses one of these banks.  Perhaps HEART was
133 /* For timer-related bits. */
222 #define HEART_MEMCFG_VALID		0x80000000	/* Bank is valid */
277  * Level 4 - Error Interrupts.
278  * Level 3 - HEART timer interrupt.
279  * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
280  * Level 1 - General device interrupts.
281  * Level 0 - General device GFX flow control interrupts.