fsl/cpm_qe/gpio.txt

1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11   "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12   "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21   one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
25 Example of four SOC GPIO banks defined as gpio-controller nodes:
27 	CPM1_PIO_A: gpio-controller@950 {
28 		#gpio-cells = <2>;
29 		compatible = "fsl,cpm1-pario-bank-a";
31 		gpio-controller;
34 	CPM1_PIO_B: gpio-controller@ab8 {
35 		#gpio-cells = <2>;
36 		compatible = "fsl,cpm1-pario-bank-b";
38 		gpio-controller;
41 	CPM1_PIO_C: gpio-controller@960 {
42 		#gpio-cells = <2>;
43 		compatible = "fsl,cpm1-pario-bank-c";
45 		fsl,cpm1-gpio-irq-mask = <0x0fff>;
47 		interrupt-parent = <&CPM_PIC>;
48 		gpio-controller;
51 	CPM1_PIO_E: gpio-controller@ac8 {
52 		#gpio-cells = <2>;
53 		compatible = "fsl,cpm1-pario-bank-e";
55 		gpio-controller;