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/linux-6.12.1/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_eqs.c27 #define GET_EQ_NUM_PAGES(eq, pg_size) \ argument
28 (ALIGN((eq)->q_len * (eq)->elem_size, pg_size) / (pg_size))
30 #define GET_EQ_NUM_ELEMS_IN_PG(eq, pg_size) ((pg_size) / (eq)->elem_size) argument
32 #define EQ_CONS_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
33 HINIC_CSR_AEQ_CONS_IDX_ADDR((eq)->q_id) : \
34 HINIC_CSR_CEQ_CONS_IDX_ADDR((eq)->q_id))
36 #define EQ_PROD_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
37 HINIC_CSR_AEQ_PROD_IDX_ADDR((eq)->q_id) : \
38 HINIC_CSR_CEQ_PROD_IDX_ADDR((eq)->q_id))
40 #define EQ_HI_PHYS_ADDR_REG(eq, pg_num) (((eq)->type == HINIC_AEQ) ? \ argument
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/
Deq.c10 #include <linux/mlx5/eq.h>
15 #include "lib/eq.h"
40 * the ci before we polled all the entries in the EQ. MLX5_NUM_SPARE_EQE is
41 * used to set the EQ size, budget must be smaller than the EQ size.
94 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) in mlx5_eq_cq_get() argument
96 struct mlx5_cq_table *table = &eq->cq_table; in mlx5_eq_cq_get()
114 struct mlx5_eq *eq = &eq_comp->core; in mlx5_eq_comp_int() local
119 eqe = next_eqe_sw(eq); in mlx5_eq_comp_int()
126 /* Make sure we read EQ entry contents after we've in mlx5_eq_comp_int()
133 cq = mlx5_eq_cq_get(eq, cqn); in mlx5_eq_comp_int()
[all …]
Dcq.c39 #include "lib/eq.h"
95 struct mlx5_eq_comp *eq; in mlx5_create_cq() local
98 eq = mlx5_eqn2comp_eq(dev, eqn); in mlx5_create_cq()
99 if (IS_ERR(eq)) in mlx5_create_cq()
100 return PTR_ERR(eq); in mlx5_create_cq()
111 cq->eq = eq; in mlx5_create_cq()
117 /* assuming CQ will be deleted before the EQ */ in mlx5_create_cq()
118 cq->tasklet_ctx.priv = &eq->tasklet_ctx; in mlx5_create_cq()
121 /* Add to comp EQ CQ tree to recv comp events */ in mlx5_create_cq()
122 err = mlx5_eq_add_cq(&eq->core, cq); in mlx5_create_cq()
[all …]
/linux-6.12.1/drivers/infiniband/hw/erdma/
Derdma_eq.c11 void notify_eq(struct erdma_eq *eq) in notify_eq() argument
13 u64 db_data = FIELD_PREP(ERDMA_EQDB_CI_MASK, eq->ci) | in notify_eq()
16 *eq->dbrec = db_data; in notify_eq()
17 writeq(db_data, eq->db); in notify_eq()
19 atomic64_inc(&eq->notify_num); in notify_eq()
22 void *get_next_valid_eqe(struct erdma_eq *eq) in get_next_valid_eqe() argument
24 u64 *eqe = get_queue_entry(eq->qbuf, eq->ci, eq->depth, EQE_SHIFT); in get_next_valid_eqe()
27 return owner ^ !!(eq->ci & eq->depth) ? eqe : NULL; in get_next_valid_eqe()
83 int erdma_eq_common_init(struct erdma_dev *dev, struct erdma_eq *eq, u32 depth) in erdma_eq_common_init() argument
87 eq->qbuf = dma_alloc_coherent(&dev->pdev->dev, buf_size, in erdma_eq_common_init()
[all …]
/linux-6.12.1/tools/testing/selftests/kexec/
Dtest_kexec_file_load.sh30 if [ $? -eq 1 ]; then
42 if [ $ima_read_policy -eq 1 ]; then
46 if [ $ret -eq 1 ]; then
52 [ $ret -eq 1 ] && log_info "IMA signature required";
66 if [ $ret -eq 1 ]; then
81 if [ $? -eq 1 ]; then
87 if [ $? -eq 0 ]; then
104 if [ $? -eq 0 ]; then
121 if [ $? -eq 0 ]; then
126 if [ $secureboot -eq 1 ] && [ $arch_policy -eq 1 ] && \
[all …]
Dtest_kexec_load.sh17 if [ $? -eq 0 ]; then
33 if [ $? -eq 0 ]; then
35 if [ $secureboot -eq 1 ] && [ $arch_policy -eq 1 ]; then
37 elif [ $ima_appraise -eq 0 -o $arch_policy -eq 0 ]; then
42 if [ $secureboot -eq 1 ] && [ $arch_policy -eq 1 ] ; then
/linux-6.12.1/drivers/infiniband/hw/mthca/
Dmthca_eq.c173 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in tavor_set_eq_ci() argument
179 * more EQ entries, and we want to avoid the exceedingly in tavor_set_eq_ci()
184 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), in tavor_set_eq_ci()
189 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in arbel_set_eq_ci() argument
194 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); in arbel_set_eq_ci()
199 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in set_eq_ci() argument
202 arbel_set_eq_ci(dev, eq, ci); in set_eq_ci()
204 tavor_set_eq_ci(dev, eq, ci); in set_eq_ci()
228 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) in get_eqe() argument
230 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; in get_eqe()
[all …]
/linux-6.12.1/sound/pci/au88x0/
Dau88x0_eq.c4 * Aureal Vortex Hardware EQ control/access.
22 The Aureal Hardware EQ is found on AU8810 and AU8830 chips only.
56 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftCoefs()
78 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightCoefs()
101 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftStates()
118 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightStates()
164 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetBypassGain()
211 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsTarget()
221 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsTarget()
231 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsCurrent()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx4/
Deq.c97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) in eq_set_ci() argument
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | in eq_set_ci()
101 eq->doorbell); in eq_set_ci()
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, in get_eqe() argument
109 /* (entry & (eq->nent - 1)) gives us a cyclic array */ in get_eqe()
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; in get_eqe()
118 …return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % … in get_eqe()
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) in next_eqe_sw() argument
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); in next_eqe_sw()
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/lib/
Deq.h7 #include <linux/mlx5/eq.h>
41 spinlock_t lock; /* To avoid irq EQ handle races with resiliency flows */
51 static inline u32 eq_get_size(struct mlx5_eq *eq) in eq_get_size() argument
53 return eq->fbc.sz_m1 + 1; in eq_get_size()
56 static inline struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) in get_eqe() argument
58 return mlx5_frag_buf_get_wqe(&eq->fbc, entry); in get_eqe()
61 static inline struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) in next_eqe_sw() argument
63 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & eq->fbc.sz_m1); in next_eqe_sw()
65 return (eqe->owner ^ (eq->cons_index >> eq->fbc.log_sz)) & 1 ? NULL : eqe; in next_eqe_sw()
68 static inline void eq_update_ci(struct mlx5_eq *eq, int arm) in eq_update_ci() argument
[all …]
/linux-6.12.1/drivers/scsi/elx/efct/
Defct_hw_queues.c14 struct hw_eq *eq = NULL; in efct_hw_init_queues() local
33 /* Create EQ */ in efct_hw_init_queues()
34 eq = efct_hw_new_eq(hw, EFCT_HW_EQ_DEPTH); in efct_hw_init_queues()
35 if (!eq) { in efct_hw_init_queues()
40 eqs[i] = eq; in efct_hw_init_queues()
44 cq = efct_hw_new_cq(eq, in efct_hw_init_queues()
59 cq = efct_hw_new_cq(eq, hw->num_qentries[SLI4_QTYPE_CQ]); in efct_hw_init_queues()
130 struct hw_eq *eq = kzalloc(sizeof(*eq), GFP_KERNEL); in efct_hw_new_eq() local
132 if (!eq) in efct_hw_new_eq()
135 eq->type = SLI4_QTYPE_EQ; in efct_hw_new_eq()
[all …]
/linux-6.12.1/drivers/mfd/
Dwm8994-regmap.c138 { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
139 { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
140 { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
141 { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
142 { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
143 { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
144 { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
145 { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
146 { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
147 { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
[all …]
/linux-6.12.1/arch/powerpc/kernel/
Dcpu_setup_6xx.S217 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
218 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
371 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
373 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
374 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
375 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
376 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
377 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
442 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
444 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
[all …]
/linux-6.12.1/tools/debugging/
Dkernel-chktaint41 if [ $taint -eq 0 ]; then
55 if [ `expr $T % 2` -eq 0 ]; then
63 if [ `expr $T % 2` -eq 0 ]; then
71 if [ `expr $T % 2` -eq 0 ]; then
79 if [ `expr $T % 2` -eq 0 ]; then
87 if [ `expr $T % 2` -eq 0 ]; then
95 if [ `expr $T % 2` -eq 0 ]; then
103 if [ `expr $T % 2` -eq 0 ]; then
111 if [ `expr $T % 2` -eq 0 ]; then
119 if [ `expr $T % 2` -eq 0 ]; then
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/en/
Dhealth.c5 #include "lib/eq.h"
52 void mlx5e_health_eq_diag_fmsg(struct mlx5_eq_comp *eq, struct devlink_fmsg *fmsg) in mlx5e_health_eq_diag_fmsg() argument
54 mlx5e_health_fmsg_named_obj_nest_start(fmsg, "EQ"); in mlx5e_health_eq_diag_fmsg()
55 devlink_fmsg_u8_pair_put(fmsg, "eqn", eq->core.eqn); in mlx5e_health_eq_diag_fmsg()
56 devlink_fmsg_u32_pair_put(fmsg, "irqn", eq->core.irqn); in mlx5e_health_eq_diag_fmsg()
57 devlink_fmsg_u32_pair_put(fmsg, "vecidx", eq->core.vecidx); in mlx5e_health_eq_diag_fmsg()
58 devlink_fmsg_u32_pair_put(fmsg, "ci", eq->core.cons_index); in mlx5e_health_eq_diag_fmsg()
59 devlink_fmsg_u32_pair_put(fmsg, "size", eq_get_size(&eq->core)); in mlx5e_health_eq_diag_fmsg()
131 int mlx5e_health_channel_eq_recover(struct net_device *dev, struct mlx5_eq_comp *eq, in mlx5e_health_channel_eq_recover() argument
136 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n", in mlx5e_health_channel_eq_recover()
[all …]
/linux-6.12.1/drivers/pci/controller/
Dpcie-iproc-msi.c59 * @eq: Event queue number
64 unsigned int eq; member
130 unsigned int eq) in iproc_msi_read_reg() argument
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
139 int eq, u32 val) in iproc_msi_write_reg() argument
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
160 static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq) in iproc_msi_eq_offset() argument
163 return eq * EQ_MEM_REGION_SIZE; in iproc_msi_eq_offset()
165 return eq * EQ_LEN * sizeof(u32); in iproc_msi_eq_offset()
303 static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) in decode_msi_hwirq() argument
[all …]
/linux-6.12.1/drivers/net/ethernet/ibm/ehea/
Dehea_qmr.c236 struct ehea_eq *eq; in ehea_create_eq() local
238 eq = kzalloc(sizeof(*eq), GFP_KERNEL); in ehea_create_eq()
239 if (!eq) in ehea_create_eq()
242 eq->adapter = adapter; in ehea_create_eq()
243 eq->attr.type = type; in ehea_create_eq()
244 eq->attr.max_nr_of_eqes = max_nr_of_eqes; in ehea_create_eq()
245 eq->attr.eqe_gen = eqe_gen; in ehea_create_eq()
246 spin_lock_init(&eq->spinlock); in ehea_create_eq()
249 &eq->attr, &eq->fw_handle); in ehea_create_eq()
255 ret = hw_queue_ctor(&eq->hw_queue, eq->attr.nr_pages, in ehea_create_eq()
[all …]
/linux-6.12.1/drivers/net/ethernet/microsoft/mana/
Dgdma_main.c225 req.log2_throttle_limit = queue->eq.log2_throttle_limit; in mana_gd_create_hw_eq()
226 req.eq_pci_msix_index = queue->eq.msix_index; in mana_gd_create_hw_eq()
236 queue->eq.disable_needed = true; in mana_gd_create_hw_eq()
282 e.eq.id = qid; in mana_gd_ring_doorbell()
283 e.eq.tail_ptr = tail_ptr; in mana_gd_ring_doorbell()
284 e.eq.arm = num_req; in mana_gd_ring_doorbell()
344 static void mana_gd_process_eqe(struct gdma_queue *eq) in mana_gd_process_eqe() argument
346 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); in mana_gd_process_eqe()
347 struct gdma_context *gc = eq->gdma_dev->gdma_context; in mana_gd_process_eqe()
348 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; in mana_gd_process_eqe()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dml26124.c76 SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
78 SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
80 SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
82 SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
84 SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
102 SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
103 SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
104 SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
105 SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
106 SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
[all …]
/linux-6.12.1/tools/testing/selftests/ftrace/test.d/ftrace/
Dfunc-filter-pid.tc25 if [ $do_function_fork -eq 1 ]; then
30 if [ $do_funcgraph_proc -eq 1 ]; then
36 if [ $do_function_fork -eq 1 ]; then
40 if [ $do_funcgraph_proc -eq 1 ]; then
62 if [ $do_function_fork -eq 1 ]; then
74 if [ $count_pid -eq 0 -o $count_other -ne 0 ]; then
81 if [ $do_function_fork -eq 0 ]; then
95 if [ $count_pid -eq 0 -o $count_other -eq 0 ]; then
/linux-6.12.1/include/linux/mlx5/
Deq.h24 mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
25 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
27 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
30 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
31 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
39 * mlx5_eq_update_cc must be called on every EQE @EQ irq handler
41 static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) in mlx5_eq_update_cc() argument
44 mlx5_eq_update_ci(eq, cc, 0); in mlx5_eq_update_cc()
/linux-6.12.1/scripts/
Dget_maintainer.pl370 if ($type eq "F" || $type eq "X") {
378 } elsif ($type eq "K") {
689 if (($self_test eq "" || $self_test =~ /\bsections\b/) &&
707 if ($type eq "S") {
710 } elsif ($type eq "F" || $type eq "N") {
712 } elsif ($type eq "M" || $type eq "R" || $type eq "L") {
734 if (($type eq "F" || $type eq "X") &&
735 ($self_test eq "" || $self_test =~ /\bpatterns\b/)) {
748 } elsif (($type eq "W" || $type eq "Q" || $type eq "B") &&
750 ($self_test eq "" || $self_test =~ /\blinks\b/)) {
[all …]
/linux-6.12.1/arch/arm64/lib/
Dcrc32.S75 csel x3, x3, x4, eq
76 csel w0, w0, w8, eq
80 csel x3, x3, x4, eq
81 csel w0, w0, w8, eq
85 csel w3, w3, w4, eq
86 csel w0, w0, w8, eq
89 csel w0, w0, w8, eq
93 csel w0, w0, w8, eq
/linux-6.12.1/arch/hexagon/lib/
Dmemset.S29 p0 = cmp.eq(r2, #0)
59 p1 = cmp.eq(r2, #1)
72 p1 = cmp.eq(r2, #2)
85 p1 = cmp.eq(r2, #4)
98 p1 = cmp.eq(r3, #1)
114 p1 = cmp.eq(r2, #8)
125 p1 = cmp.eq(r2, #4)
136 p1 = cmp.eq(r2, #2)
180 p1 = cmp.eq(r2, #1)
196 p0 = cmp.eq(r2, #2)
[all …]
/linux-6.12.1/drivers/infiniband/hw/mlx5/
Dodp.c43 #include <linux/mlx5/eq.h>
87 struct mlx5_ib_pf_eq *eq; member
1475 * the eq, switch to the dummy pagefault for the rest of the in mlx5_ib_mr_rdma_pfault_handler()
1586 struct mlx5_ib_pf_eq *eq = pfault->eq; in mlx5_ib_eqe_pf_action() local
1588 mlx5_ib_pfault(eq->dev, pfault); in mlx5_ib_eqe_pf_action()
1589 mempool_free(pfault, eq->pool); in mlx5_ib_eqe_pf_action()
1593 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq) in mlx5_ib_eq_pf_process() argument
1600 while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) { in mlx5_ib_eq_pf_process()
1601 pfault = mempool_alloc(eq->pool, GFP_ATOMIC); in mlx5_ib_eq_pf_process()
1603 schedule_work(&eq->work); in mlx5_ib_eq_pf_process()
[all …]

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