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/linux-6.12.1/drivers/clk/qcom/
Dclk-spmi-pmic-div.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
24 struct clkdiv { struct
33 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) in to_clkdiv() argument
35 return container_of(hw, struct clkdiv, hw); in to_clkdiv()
43 return 1 << (div_factor - 1); in div_factor_to_div()
51 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
61 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
65 unsigned int ns = clkdiv->cxo_period_ns; in __spmi_pmic_clkdiv_set_enable_state()
[all …]
/linux-6.12.1/drivers/spi/
Dspi-cavium.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define OCTEON_SPI_CFG(x) (x->regs.config)
27 #define OCTEON_SPI_STS(x) (x->regs.status)
28 #define OCTEON_SPI_TX(x) (x->regs.tx)
29 #define OCTEON_SPI_DAT0(x) (x->regs.data)
46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
[all …]
Dspi-cavium.c14 #include "spi-cavium.h"
24 mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p)); in octeon_spi_wait_ready()
33 struct spi_device *spi = msg->spi; in octeon_spi_do_transfer()
36 unsigned int clkdiv; in octeon_spi_do_transfer() local
44 mode = spi->mode; in octeon_spi_do_transfer()
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
61 p->cs_enax |= 1ull << (12 + spi_get_chipselect(spi, 0)); in octeon_spi_do_transfer()
62 mpi_cfg.u64 |= p->cs_enax; in octeon_spi_do_transfer()
64 if (mpi_cfg.u64 != p->last_cfg) { in octeon_spi_do_transfer()
[all …]
Dspi-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
21 #define DRV_NAME "spi-pci1xxxx"
105 /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
136 u8 clkdiv; member
197 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
198 return readl(par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
212 writel(0x0, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
217 struct pci_dev *pdev = spi_bus->dev; in pci1xxxx_check_spi_can_dma()
228 dev_err(&pdev->dev, "Error failed to acquire syslock\n"); in pci1xxxx_check_spi_can_dma()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,spmi-clkdiv.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Stephen Boyd <sboyd@kernel.org>
20 const: qcom,spmi-clkdiv
27 - description: Board XO source
29 clock-names:
31 - const: xo
[all …]
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
[all …]
Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
31 - compatible
[all …]
/linux-6.12.1/drivers/hwtracing/intel_th/
Dpti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Intel Corporation.
27 unsigned int clkdiv; member
46 return -EINVAL; in pti_width_mode()
54 return scnprintf(buf, PAGE_SIZE, "%d\n", pti_mode[pti->mode]); in mode_show()
72 pti->mode = ret; in mode_store()
85 return scnprintf(buf, PAGE_SIZE, "%d\n", pti->freeclk); in freerunning_clock_show()
100 pti->freeclk = !!val; in freerunning_clock_store()
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
129 return -EINVAL; in clock_divider_store()
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Demev2.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <533000000>;
[all …]
/linux-6.12.1/drivers/pwm/
Dpwm-tiehrpwm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
144 * set_prescale_div - Set up the prescaler divider function
152 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
154 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
160 * CLKDIVIDER = (1), if clkdiv == 0 *OR* in set_prescale_div()
161 * (2 * clkdiv), if clkdiv != 0 in set_prescale_div()
167 *prescale_div = (1 << clkdiv) * in set_prescale_div()
170 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
195 if (pc->polarity[chan] == PWM_POLARITY_INVERSED) in configure_polarity()
[all …]
Dpwm-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
44 * struct pwm_mediatek_chip - struct representing PWM chip
79 ret = clk_prepare_enable(pc->clk_top); in pwm_mediatek_clk_enable()
83 ret = clk_prepare_enable(pc->clk_main); in pwm_mediatek_clk_enable()
87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_enable()
94 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_enable()
96 clk_disable_unprepare(pc->clk_top); in pwm_mediatek_clk_enable()
106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_disable()
107 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_disable()
108 clk_disable_unprepare(pc->clk_top); in pwm_mediatek_clk_disable()
[all …]
/linux-6.12.1/drivers/w1/masters/
Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
22 # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
45 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
53 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
55 /* PST bit is valid after the RPP bit is self-cleared */ in mxc_w1_ds2_reset_bus()
73 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
81 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
83 /* RDST bit is valid after the WR1/RD bit is self-cleared */ in mxc_w1_ds2_touch_bit()
95 unsigned int clkdiv; in mxc_w1_probe() local
[all …]
/linux-6.12.1/sound/soc/adi/
Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
80 unsigned int clkdiv, stat; in axi_spdif_hw_params() local
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
99 clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dadau1701.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
99 #define ADAU1707_CLKDIV_UNSET (-1U)
191 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_write()
193 return -EINVAL; in adau1701_reg_write()
198 for (i = size + 1; i >= 2; --i) { in adau1701_reg_write()
209 return -EIO; in adau1701_reg_write()
222 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_read()
224 return -EINVAL; in adau1701_reg_read()
229 msgs[0].addr = client->addr; in adau1701_reg_read()
[all …]
/linux-6.12.1/drivers/iio/adc/
Dlpc18xx_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * - Hardware triggers
9 * - Burst mode
10 * - Interrupts
11 * - DMA
74 reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; in lpc18xx_adc_read_chan()
75 writel(reg, adc->base + LPC18XX_ADC_CR); in lpc18xx_adc_read_chan()
77 ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, in lpc18xx_adc_read_chan()
80 dev_warn(adc->dev, "adc read timed out\n"); in lpc18xx_adc_read_chan()
95 mutex_lock(&adc->lock); in lpc18xx_adc_read_raw()
[all …]
/linux-6.12.1/drivers/gpu/drm/exynos/
Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "regs-decon7.h"
62 {.compatible = "samsung,exynos7-decon"},
86 struct decon_context *ctx = crtc->ctx; in decon_wait_for_vblank()
88 if (ctx->suspended) in decon_wait_for_vblank()
91 atomic_set(&ctx->wait_vsync_event, 1); in decon_wait_for_vblank()
97 if (!wait_event_timeout(ctx->wait_vsync_queue, in decon_wait_for_vblank()
98 !atomic_read(&ctx->wait_vsync_event), in decon_wait_for_vblank()
100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in decon_wait_for_vblank()
105 struct decon_context *ctx = crtc->ctx; in decon_clear_channels()
[all …]
Dexynos_drm_fimd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
63 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
65 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
194 u32 clkdiv; member
202 { .compatible = "samsung,s3c6400-fimd",
204 { .compatible = "samsung,s5pv210-fimd",
206 { .compatible = "samsung,exynos3250-fimd",
208 { .compatible = "samsung,exynos4210-fimd",
210 { .compatible = "samsung,exynos5250-fimd",
212 { .compatible = "samsung,exynos5420-fimd",
[all …]
/linux-6.12.1/drivers/gpu/drm/tilcdc/
Dtilcdc_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
65 struct drm_device *dev = crtc->dev; in set_scanout()
66 struct tilcdc_drm_private *priv = dev->dev_private; in set_scanout()
73 start = gem->dma_addr + fb->offsets[0] + in set_scanout()
74 crtc->y * fb->pitches[0] + in set_scanout()
75 crtc->x * fb->format->cpp[0]; in set_scanout()
77 end = start + (crtc->mode.vdisplay * fb->pitches[0]); in set_scanout()
84 if (priv->rev == 1) in set_scanout()
85 end -= 1; in set_scanout()
[all …]
/linux-6.12.1/drivers/mmc/host/
Dsunplus-mmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Li-hao Kuo <lhjeff911@gmail.com>
11 #include <linux/dma-mapping.h>
18 #include <linux/mmc/slot-gpio.h>
180 return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state, in spmmc_wait_finish()
189 return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status, in spmmc_wait_sdstatus()
202 if (!(cmd->flags & MMC_RSP_PRESENT)) in spmmc_get_rsp()
204 if (cmd->flags & MMC_RSP_136) { in spmmc_get_rsp()
207 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); in spmmc_get_rsp()
208 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; in spmmc_get_rsp()
[all …]
Dsh_mmcif.c1 // SPDX-License-Identifier: GPL-2.0
23 * request- and stage-specific handler methods.
39 #include <linux/dma-mapping.h>
46 #include <linux/mmc/slot-gpio.h>
240 u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */
250 { .compatible = "renesas,sh-mmcif" },
255 #define sh_mmcif_host_to_dev(host) (&host->pd->dev)
260 writel(val | readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitset()
266 writel(~val & readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitclr()
272 struct mmc_request *mrq = host->mrq; in sh_mmcif_dma_complete()
[all …]
Datmel-mci.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2008 Atmel Corporation
12 #include <linux/dma-mapping.h>
63 #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
72 #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
73 #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
74 #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
80 #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
81 #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
93 #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
[all …]
/linux-6.12.1/arch/powerpc/platforms/52xx/
Dmpc52xx_common.c25 { .compatible = "fsl,mpc5200-xlb", },
26 { .compatible = "mpc5200-xlb", },
30 { .compatible = "fsl,mpc5200-immr", },
31 { .compatible = "fsl,mpc5200b-immr", },
32 { .compatible = "simple-bus", },
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
77 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
81 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
110 { .compatible = "fsl,mpc5200-gpt", },
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/frequency/
Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/linux-6.12.1/arch/mips/lantiq/falcon/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
48 (0x2 << 24) | /* CLKDIV */ in machine_restart()
/linux-6.12.1/drivers/i2c/busses/
Di2c-ibm_iic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/i2c/busses/i2c-ibm_iic.h
15 * Copyright 2000-2003 MontaVista Software Inc.
33 u8 clkdiv; member

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