Lines Matching +full:clkdiv +full:- +full:-
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
21 #define DRV_NAME "spi-pci1xxxx"
105 /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
136 u8 clkdiv; member
197 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
198 return readl(par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
212 writel(0x0, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
217 struct pci_dev *pdev = spi_bus->dev; in pci1xxxx_check_spi_can_dma()
228 dev_err(&pdev->dev, "Error failed to acquire syslock\n"); in pci1xxxx_check_spi_can_dma()
232 regval = readl(spi_bus->reg_base + DEV_REV_REG); in pci1xxxx_check_spi_can_dma()
233 spi_bus->dev_rev = regval & DEV_REV_MASK; in pci1xxxx_check_spi_can_dma()
234 if (spi_bus->dev_rev >= 0xC0) { in pci1xxxx_check_spi_can_dma()
235 regval = readl(spi_bus->reg_base + in pci1xxxx_check_spi_can_dma()
246 if (spi_bus->dev_rev < 0xC0 || pf_num) in pci1xxxx_check_spi_can_dma()
247 return -EOPNOTSUPP; in pci1xxxx_check_spi_can_dma()
255 dev_warn(&pdev->dev, "Error MSI Interrupt not supported, will operate in PIO mode\n"); in pci1xxxx_check_spi_can_dma()
256 return -EOPNOTSUPP; in pci1xxxx_check_spi_can_dma()
259 spi_bus->dma_offset_bar = pcim_iomap(pdev, 2, pci_resource_len(pdev, 2)); in pci1xxxx_check_spi_can_dma()
260 if (!spi_bus->dma_offset_bar) { in pci1xxxx_check_spi_can_dma()
261 dev_warn(&pdev->dev, "Error failed to map dma bar, will operate in PIO mode\n"); in pci1xxxx_check_spi_can_dma()
262 return -EOPNOTSUPP; in pci1xxxx_check_spi_can_dma()
265 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { in pci1xxxx_check_spi_can_dma()
266 dev_warn(&pdev->dev, "Error failed to set DMA mask, will operate in PIO mode\n"); in pci1xxxx_check_spi_can_dma()
267 pcim_iounmap(pdev, spi_bus->dma_offset_bar); in pci1xxxx_check_spi_can_dma()
268 spi_bus->dma_offset_bar = NULL; in pci1xxxx_check_spi_can_dma()
269 return -EOPNOTSUPP; in pci1xxxx_check_spi_can_dma()
284 spin_lock_init(&spi_bus->dma_reg_lock); in pci1xxxx_spi_dma_init()
286 writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN); in pci1xxxx_spi_dma_init()
287 writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN); in pci1xxxx_spi_dma_init()
288 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_HIGH); in pci1xxxx_spi_dma_init()
289 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_HIGH); in pci1xxxx_spi_dma_init()
290 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_HIGH); in pci1xxxx_spi_dma_init()
291 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_HIGH); in pci1xxxx_spi_dma_init()
292 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_LOW); in pci1xxxx_spi_dma_init()
293 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_LOW); in pci1xxxx_spi_dma_init()
294 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_LOW); in pci1xxxx_spi_dma_init()
295 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_LOW); in pci1xxxx_spi_dma_init()
296 writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA); in pci1xxxx_spi_dma_init()
297 writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA); in pci1xxxx_spi_dma_init()
298 dma_set_max_seg_size(&spi_bus->dev->dev, PCI1XXXX_SPI_BUFFER_SIZE); in pci1xxxx_spi_dma_init()
299 spi_bus->can_dma = true; in pci1xxxx_spi_dma_init()
305 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi->controller); in pci1xxxx_spi_set_cs()
306 struct pci1xxxx_spi *par = p->parent; in pci1xxxx_spi_set_cs()
310 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_set_cs()
318 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_set_cs()
348 if (!p->hw_inst) in pci1xxxx_spi_setup_dma_to_io()
349 base = p->parent->dma_offset_bar + SPI_DMA_CH0_RD_BASE; in pci1xxxx_spi_setup_dma_to_io()
351 base = p->parent->dma_offset_bar + SPI_DMA_CH1_RD_BASE; in pci1xxxx_spi_setup_dma_to_io()
358 writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)), in pci1xxxx_spi_setup_dma_to_io()
360 writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)), in pci1xxxx_spi_setup_dma_to_io()
369 if (!p->hw_inst) in pci1xxxx_spi_setup_dma_from_io()
370 base = p->parent->dma_offset_bar + SPI_DMA_CH0_WR_BASE; in pci1xxxx_spi_setup_dma_from_io()
372 base = p->parent->dma_offset_bar + SPI_DMA_CH1_WR_BASE; in pci1xxxx_spi_setup_dma_from_io()
378 writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)), in pci1xxxx_spi_setup_dma_from_io()
380 writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)), in pci1xxxx_spi_setup_dma_from_io()
385 u8 clkdiv, u32 len) in pci1xxxx_spi_setup() argument
389 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_spi_setup()
397 regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv); in pci1xxxx_spi_setup()
398 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_spi_setup()
405 regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_start_spi_xfer()
407 writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_start_spi_xfer()
414 struct pci1xxxx_spi *par = p->parent; in pci1xxxx_spi_transfer_with_io()
422 u8 clkdiv; in pci1xxxx_spi_transfer_with_io() local
424 p->spi_xfer_in_progress = true; in pci1xxxx_spi_transfer_with_io()
425 p->bytes_recvd = 0; in pci1xxxx_spi_transfer_with_io()
426 clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz); in pci1xxxx_spi_transfer_with_io()
427 tx_buf = xfer->tx_buf; in pci1xxxx_spi_transfer_with_io()
428 rx_buf = xfer->rx_buf; in pci1xxxx_spi_transfer_with_io()
429 transfer_len = xfer->len; in pci1xxxx_spi_transfer_with_io()
430 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_io()
431 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_io()
443 (loop_iter == loop_count - 1)) in pci1xxxx_spi_transfer_with_io()
446 reinit_completion(&p->spi_xfer_done); in pci1xxxx_spi_transfer_with_io()
447 memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst), in pci1xxxx_spi_transfer_with_io()
450 pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len); in pci1xxxx_spi_transfer_with_io()
451 pci1xxxx_start_spi_xfer(p, p->hw_inst); in pci1xxxx_spi_transfer_with_io()
454 result = wait_for_completion_timeout(&p->spi_xfer_done, in pci1xxxx_spi_transfer_with_io()
457 return -ETIMEDOUT; in pci1xxxx_spi_transfer_with_io()
460 memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base + in pci1xxxx_spi_transfer_with_io()
461 SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len); in pci1xxxx_spi_transfer_with_io()
466 p->spi_xfer_in_progress = false; in pci1xxxx_spi_transfer_with_io()
476 struct pci1xxxx_spi *par = p->parent; in pci1xxxx_spi_transfer_with_dma()
482 p->spi_xfer_in_progress = true; in pci1xxxx_spi_transfer_with_dma()
483 p->tx_sgl = xfer->tx_sg.sgl; in pci1xxxx_spi_transfer_with_dma()
484 p->rx_sgl = xfer->rx_sg.sgl; in pci1xxxx_spi_transfer_with_dma()
485 p->rx_buf = xfer->rx_buf; in pci1xxxx_spi_transfer_with_dma()
486 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
487 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
489 if (!xfer->tx_buf || !p->tx_sgl) { in pci1xxxx_spi_transfer_with_dma()
490 ret = -EINVAL; in pci1xxxx_spi_transfer_with_dma()
493 p->xfer = xfer; in pci1xxxx_spi_transfer_with_dma()
494 p->mode = spi->mode; in pci1xxxx_spi_transfer_with_dma()
495 p->clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz); in pci1xxxx_spi_transfer_with_dma()
496 p->bytes_recvd = 0; in pci1xxxx_spi_transfer_with_dma()
497 p->rx_buf = xfer->rx_buf; in pci1xxxx_spi_transfer_with_dma()
498 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
499 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
501 tx_dma_addr = sg_dma_address(p->tx_sgl); in pci1xxxx_spi_transfer_with_dma()
502 rx_dma_addr = sg_dma_address(p->rx_sgl); in pci1xxxx_spi_transfer_with_dma()
503 p->tx_sgl_len = sg_dma_len(p->tx_sgl); in pci1xxxx_spi_transfer_with_dma()
504 p->rx_sgl_len = sg_dma_len(p->rx_sgl); in pci1xxxx_spi_transfer_with_dma()
505 pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); in pci1xxxx_spi_transfer_with_dma()
506 pci1xxxx_spi_setup_dma_to_io(p, (tx_dma_addr), p->tx_sgl_len); in pci1xxxx_spi_transfer_with_dma()
508 pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len); in pci1xxxx_spi_transfer_with_dma()
509 writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG); in pci1xxxx_spi_transfer_with_dma()
511 reinit_completion(&p->spi_xfer_done); in pci1xxxx_spi_transfer_with_dma()
513 ret = wait_for_completion_timeout(&p->spi_xfer_done, PCI1XXXX_SPI_TIMEOUT); in pci1xxxx_spi_transfer_with_dma()
515 ret = -ETIMEDOUT; in pci1xxxx_spi_transfer_with_dma()
516 if (p->dma_aborted_rd) { in pci1xxxx_spi_transfer_with_dma()
518 par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN); in pci1xxxx_spi_transfer_with_dma()
524 ret = readl_poll_timeout(par->dma_offset_bar + in pci1xxxx_spi_transfer_with_dma()
528 ret = -ECANCELED; in pci1xxxx_spi_transfer_with_dma()
532 par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN); in pci1xxxx_spi_transfer_with_dma()
533 p->dma_aborted_rd = false; in pci1xxxx_spi_transfer_with_dma()
534 ret = -ECANCELED; in pci1xxxx_spi_transfer_with_dma()
536 if (p->dma_aborted_wr) { in pci1xxxx_spi_transfer_with_dma()
538 par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN); in pci1xxxx_spi_transfer_with_dma()
545 ret = readl_poll_timeout(par->dma_offset_bar + in pci1xxxx_spi_transfer_with_dma()
549 ret = -ECANCELED; in pci1xxxx_spi_transfer_with_dma()
554 par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN); in pci1xxxx_spi_transfer_with_dma()
555 p->dma_aborted_wr = false; in pci1xxxx_spi_transfer_with_dma()
556 ret = -ECANCELED; in pci1xxxx_spi_transfer_with_dma()
563 p->spi_xfer_in_progress = false; in pci1xxxx_spi_transfer_with_dma()
584 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_io()
587 if (p->parent->can_dma && p->rx_buf) in pci1xxxx_spi_isr_io()
588 writel(p->hw_inst, p->parent->dma_offset_bar + in pci1xxxx_spi_isr_io()
591 complete(&p->parent->spi_int[p->hw_inst]->spi_xfer_done); in pci1xxxx_spi_isr_io()
594 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_io()
604 p->tx_sgl = sg_next(p->tx_sgl); in pci1xxxx_spi_setup_next_dma_transfer()
605 if (p->rx_sgl) in pci1xxxx_spi_setup_next_dma_transfer()
606 p->rx_sgl = sg_next(p->rx_sgl); in pci1xxxx_spi_setup_next_dma_transfer()
607 if (!p->tx_sgl) { in pci1xxxx_spi_setup_next_dma_transfer()
609 complete(&p->spi_xfer_done); in pci1xxxx_spi_setup_next_dma_transfer()
611 tx_dma_addr = sg_dma_address(p->tx_sgl); in pci1xxxx_spi_setup_next_dma_transfer()
612 prev_len = p->tx_sgl_len; in pci1xxxx_spi_setup_next_dma_transfer()
613 p->tx_sgl_len = sg_dma_len(p->tx_sgl); in pci1xxxx_spi_setup_next_dma_transfer()
614 if (prev_len != p->tx_sgl_len) in pci1xxxx_spi_setup_next_dma_transfer()
615 pci1xxxx_spi_setup(p->parent, in pci1xxxx_spi_setup_next_dma_transfer()
616 p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); in pci1xxxx_spi_setup_next_dma_transfer()
617 pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len); in pci1xxxx_spi_setup_next_dma_transfer()
618 if (p->rx_sgl) { in pci1xxxx_spi_setup_next_dma_transfer()
619 rx_dma_addr = sg_dma_address(p->rx_sgl); in pci1xxxx_spi_setup_next_dma_transfer()
620 p->rx_sgl_len = sg_dma_len(p->rx_sgl); in pci1xxxx_spi_setup_next_dma_transfer()
621 pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len); in pci1xxxx_spi_setup_next_dma_transfer()
623 writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG); in pci1xxxx_spi_setup_next_dma_transfer()
634 spin_lock_irqsave(&p->parent->dma_reg_lock, flags); in pci1xxxx_spi_isr_dma()
636 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS); in pci1xxxx_spi_isr_dma()
645 p->dma_aborted_rd = true; in pci1xxxx_spi_isr_dma()
648 writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR); in pci1xxxx_spi_isr_dma()
651 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS); in pci1xxxx_spi_isr_dma()
654 pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI0]); in pci1xxxx_spi_isr_dma()
657 pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI1]); in pci1xxxx_spi_isr_dma()
662 p->dma_aborted_wr = true; in pci1xxxx_spi_isr_dma()
665 writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR); in pci1xxxx_spi_isr_dma()
666 spin_unlock_irqrestore(&p->parent->dma_reg_lock, flags); in pci1xxxx_spi_isr_dma()
669 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_dma()
671 writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG); in pci1xxxx_spi_isr_dma()
674 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_dma()
682 if (p->spi_host->can_dma(p->spi_host, NULL, p->xfer)) in pci1xxxx_spi_isr()
693 struct pci1xxxx_spi *par = p->parent; in pci1xxxx_spi_can_dma()
695 return par->can_dma; in pci1xxxx_spi_can_dma()
702 struct device *dev = &pdev->dev; in pci1xxxx_spi_probe()
708 hw_inst_cnt = ent->driver_data & 0x0f; in pci1xxxx_spi_probe()
709 start = (ent->driver_data & 0xf0) >> 4; in pci1xxxx_spi_probe()
715 spi_bus = devm_kzalloc(&pdev->dev, in pci1xxxx_spi_probe()
719 return -ENOMEM; in pci1xxxx_spi_probe()
721 spi_bus->dev = pdev; in pci1xxxx_spi_probe()
722 spi_bus->total_hw_instances = hw_inst_cnt; in pci1xxxx_spi_probe()
726 spi_bus->spi_int[iter] = devm_kzalloc(&pdev->dev, in pci1xxxx_spi_probe()
729 if (!spi_bus->spi_int[iter]) in pci1xxxx_spi_probe()
730 return -ENOMEM; in pci1xxxx_spi_probe()
731 spi_sub_ptr = spi_bus->spi_int[iter]; in pci1xxxx_spi_probe()
732 spi_sub_ptr->spi_host = devm_spi_alloc_host(dev, sizeof(struct spi_controller)); in pci1xxxx_spi_probe()
733 if (!spi_sub_ptr->spi_host) in pci1xxxx_spi_probe()
734 return -ENOMEM; in pci1xxxx_spi_probe()
736 spi_sub_ptr->parent = spi_bus; in pci1xxxx_spi_probe()
737 spi_sub_ptr->spi_xfer_in_progress = false; in pci1xxxx_spi_probe()
742 return -ENOMEM; in pci1xxxx_spi_probe()
746 return -ENOMEM; in pci1xxxx_spi_probe()
748 spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); in pci1xxxx_spi_probe()
749 if (!spi_bus->reg_base) { in pci1xxxx_spi_probe()
750 ret = -EINVAL; in pci1xxxx_spi_probe()
757 dev_err(&pdev->dev, "Error allocating MSI vectors\n"); in pci1xxxx_spi_probe()
761 init_completion(&spi_sub_ptr->spi_xfer_done); in pci1xxxx_spi_probe()
762 /* Initialize Interrupts - SPI_INT */ in pci1xxxx_spi_probe()
763 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe()
764 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); in pci1xxxx_spi_probe()
766 writel(regval, spi_bus->reg_base + in pci1xxxx_spi_probe()
767 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); in pci1xxxx_spi_probe()
768 spi_sub_ptr->irq = pci_irq_vector(pdev, 0); in pci1xxxx_spi_probe()
770 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq, in pci1xxxx_spi_probe()
774 dev_err(&pdev->dev, "Unable to request irq : %d", in pci1xxxx_spi_probe()
775 spi_sub_ptr->irq); in pci1xxxx_spi_probe()
776 ret = -ENODEV; in pci1xxxx_spi_probe()
780 ret = pci1xxxx_spi_dma_init(spi_bus, spi_sub_ptr->irq); in pci1xxxx_spi_probe()
781 if (ret && ret != -EOPNOTSUPP) in pci1xxxx_spi_probe()
785 regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); in pci1xxxx_spi_probe()
791 writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); in pci1xxxx_spi_probe()
794 spi_sub_ptr->hw_inst = start++; in pci1xxxx_spi_probe()
797 init_completion(&spi_sub_ptr->spi_xfer_done); in pci1xxxx_spi_probe()
798 /* Initialize Interrupts - SPI_INT */ in pci1xxxx_spi_probe()
799 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe()
800 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); in pci1xxxx_spi_probe()
802 writel(regval, spi_bus->reg_base + in pci1xxxx_spi_probe()
803 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); in pci1xxxx_spi_probe()
804 spi_sub_ptr->irq = pci_irq_vector(pdev, iter); in pci1xxxx_spi_probe()
805 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq, in pci1xxxx_spi_probe()
809 dev_err(&pdev->dev, "Unable to request irq : %d", in pci1xxxx_spi_probe()
810 spi_sub_ptr->irq); in pci1xxxx_spi_probe()
811 ret = -ENODEV; in pci1xxxx_spi_probe()
816 spi_host = spi_sub_ptr->spi_host; in pci1xxxx_spi_probe()
817 spi_host->num_chipselect = SPI_CHIP_SEL_COUNT; in pci1xxxx_spi_probe()
818 spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL | in pci1xxxx_spi_probe()
820 spi_host->can_dma = pci1xxxx_spi_can_dma; in pci1xxxx_spi_probe()
821 spi_host->transfer_one = pci1xxxx_spi_transfer_one; in pci1xxxx_spi_probe()
823 spi_host->set_cs = pci1xxxx_spi_set_cs; in pci1xxxx_spi_probe()
824 spi_host->bits_per_word_mask = SPI_BPW_MASK(8); in pci1xxxx_spi_probe()
825 spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ; in pci1xxxx_spi_probe()
826 spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ; in pci1xxxx_spi_probe()
827 spi_host->flags = SPI_CONTROLLER_MUST_TX; in pci1xxxx_spi_probe()
849 regval = readl(spi_ptr->reg_base + in store_restore_config()
850 SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst)); in store_restore_config()
852 spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7; in store_restore_config()
853 regval = readl(spi_ptr->reg_base + in store_restore_config()
854 SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst)); in store_restore_config()
856 spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1; in store_restore_config()
858 regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); in store_restore_config()
860 regval |= (spi_sub_ptr->prev_val.dev_sel << 25); in store_restore_config()
862 spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); in store_restore_config()
863 writel((spi_sub_ptr->prev_val.msi_vector_sel << 4), in store_restore_config()
864 spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst)); in store_restore_config()
875 for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) { in pci1xxxx_spi_resume()
876 spi_sub_ptr = spi_ptr->spi_int[iter]; in pci1xxxx_spi_resume()
877 spi_controller_resume(spi_sub_ptr->spi_host); in pci1xxxx_spi_resume()
878 writel(regval, spi_ptr->reg_base + in pci1xxxx_spi_resume()
895 for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) { in pci1xxxx_spi_suspend()
896 spi_sub_ptr = spi_ptr->spi_int[iter]; in pci1xxxx_spi_suspend()
898 while (spi_sub_ptr->spi_xfer_in_progress) in pci1xxxx_spi_suspend()
903 spi_controller_suspend(spi_sub_ptr->spi_host); in pci1xxxx_spi_suspend()
904 writel(reg1, spi_ptr->reg_base + in pci1xxxx_spi_suspend()