25 	{ .compatible = "fsl,mpc5200-xlb", },
26 	{ .compatible = "mpc5200-xlb", },
30 	{ .compatible = "fsl,mpc5200-immr", },
31 	{ .compatible = "fsl,mpc5200b-immr", },
32 	{ .compatible = "simple-bus", },
71 	out_be32(&xlb->master_pri_enable, 0xff);  in mpc5200_setup_xlb_arbiter()
72 	out_be32(&xlb->master_priority, 0x11111111);  in mpc5200_setup_xlb_arbiter()
77 	 *  transaction and re-enable it afterwards ...)  in mpc5200_setup_xlb_arbiter()
81 		out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS);  in mpc5200_setup_xlb_arbiter()
110 	{ .compatible = "fsl,mpc5200-gpt", },
111 	{ .compatible = "mpc5200-gpt", }, /* old */
115 	{ .compatible = "fsl,mpc5200-cdm", },
116 	{ .compatible = "mpc5200-cdm", }, /* old */
120 	{ .compatible = "fsl,mpc5200-gpio", },
124 	{ .compatible = "fsl,mpc5200-gpio-wkup", },
139 	 * on a gpt0, so check has-wdt property before mapping.  in mpc52xx_map_common_devices()
142 		if (of_property_read_bool(np, "fsl,has-wdt") ||  in mpc52xx_map_common_devices()
143 		    of_property_read_bool(np, "has-wdt")) {  in mpc52xx_map_common_devices()
170  * @clkdiv: clock divider value to put into CDM PSC register.
172 int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)  in mpc52xx_set_psc_clkdiv()  argument
181 		return -ENODEV;  in mpc52xx_set_psc_clkdiv()
183 	mclken_div = 0x8000 | (clkdiv & 0x1FF);  in mpc52xx_set_psc_clkdiv()
185 	case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;  in mpc52xx_set_psc_clkdiv()
186 	case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;  in mpc52xx_set_psc_clkdiv()
187 	case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;  in mpc52xx_set_psc_clkdiv()
188 	case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;  in mpc52xx_set_psc_clkdiv()
190 		return -ENODEV;  in mpc52xx_set_psc_clkdiv()
196 	val = in_be32(&mpc52xx_cdm->clk_enables);  in mpc52xx_set_psc_clkdiv()
197 	out_be32(&mpc52xx_cdm->clk_enables, val | mask);  in mpc52xx_set_psc_clkdiv()
205  * mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
214 		out_be32(&mpc52xx_wdt->mode, 0x00000000);  in mpc52xx_restart()
215 		out_be32(&mpc52xx_wdt->count, 0x000000ff);  in mpc52xx_restart()
216 		out_be32(&mpc52xx_wdt->mode, 0x00009004);  in mpc52xx_restart()
249 		return -ENODEV;  in mpc5200_psc_ac97_gpio_reset()
266 		       "cold-reset will be performed\n");  in mpc5200_psc_ac97_gpio_reset()
267 		return -ENODEV;  in mpc5200_psc_ac97_gpio_reset()
272 	/* Reconfigure pin-muxing to gpio */  in mpc5200_psc_ac97_gpio_reset()
273 	mux = in_be32(&simple_gpio->port_config);  in mpc5200_psc_ac97_gpio_reset()
274 	out_be32(&simple_gpio->port_config, mux & (~gpio));  in mpc5200_psc_ac97_gpio_reset()
277 	setbits8(&wkup_gpio->wkup_gpioe, reset);  in mpc5200_psc_ac97_gpio_reset()
278 	setbits32(&simple_gpio->simple_gpioe, sync | out);  in mpc5200_psc_ac97_gpio_reset()
280 	setbits8(&wkup_gpio->wkup_ddr, reset);  in mpc5200_psc_ac97_gpio_reset()
281 	setbits32(&simple_gpio->simple_ddr, sync | out);  in mpc5200_psc_ac97_gpio_reset()
284 	clrbits32(&simple_gpio->simple_dvo, sync | out);  in mpc5200_psc_ac97_gpio_reset()
285 	clrbits8(&wkup_gpio->wkup_dvo, reset);  in mpc5200_psc_ac97_gpio_reset()
291 	setbits8(&wkup_gpio->wkup_dvo, reset);  in mpc5200_psc_ac97_gpio_reset()
297 	/* Restore pin-muxing */  in mpc5200_psc_ac97_gpio_reset()
298 	out_be32(&simple_gpio->port_config, mux);  in mpc5200_psc_ac97_gpio_reset()