| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | cirrus,lochnagar.yaml | 86 gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk,
88 codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
89 codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat,
90 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
92 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
93 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
94 psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
95 psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat,
96 gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
98 gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
[all …]
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| /linux-6.12.1/drivers/media/dvb-frontends/ |
| D | z0194a.h | 16 u8 bclk = 0; in sharp_z0194a_set_symbol_rate() local
19 aclk = 0xb7; bclk = 0x47; } in sharp_z0194a_set_symbol_rate()
21 aclk = 0xb7; bclk = 0x4b; } in sharp_z0194a_set_symbol_rate()
23 aclk = 0xb7; bclk = 0x4f; } in sharp_z0194a_set_symbol_rate()
25 aclk = 0xb7; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
27 aclk = 0xb6; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
29 aclk = 0xb4; bclk = 0x51; } in sharp_z0194a_set_symbol_rate()
32 stv0299_writereg(fe, 0x14, bclk); in sharp_z0194a_set_symbol_rate()
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| D | bsbe1.h | 37 u8 bclk = 0; in alps_bsbe1_set_symbol_rate() local
39 if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; } in alps_bsbe1_set_symbol_rate()
40 else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; } in alps_bsbe1_set_symbol_rate()
41 else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; } in alps_bsbe1_set_symbol_rate()
42 else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
43 else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
44 else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; } in alps_bsbe1_set_symbol_rate()
47 stv0299_writereg(fe, 0x14, bclk); in alps_bsbe1_set_symbol_rate()
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| D | bsru6.h | 56 u8 bclk = 0; in alps_bsru6_set_symbol_rate() local
60 bclk = 0x47; in alps_bsru6_set_symbol_rate()
63 bclk = 0x4b; in alps_bsru6_set_symbol_rate()
66 bclk = 0x4f; in alps_bsru6_set_symbol_rate()
69 bclk = 0x53; in alps_bsru6_set_symbol_rate()
72 bclk = 0x53; in alps_bsru6_set_symbol_rate()
75 bclk = 0x51; in alps_bsru6_set_symbol_rate()
79 stv0299_writereg(fe, 0x14, bclk); in alps_bsru6_set_symbol_rate()
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| /linux-6.12.1/Documentation/sound/soc/ |
| D | dai.rst | 15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
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| D | clocking.rst | 25 as BCLK). This clock is used to drive the digital audio data across the link
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
39 it is best to configure BCLK to the lowest possible speed (depending on your
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| /linux-6.12.1/drivers/media/pci/mantis/ |
| D | mantis_vp1033.c | 110 u8 bclk = 0; in lgtdqcs001f_set_symbol_rate() local
114 bclk = 0x47; in lgtdqcs001f_set_symbol_rate()
117 bclk = 0x4b; in lgtdqcs001f_set_symbol_rate()
120 bclk = 0x4f; in lgtdqcs001f_set_symbol_rate()
123 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
126 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
129 bclk = 0x51; in lgtdqcs001f_set_symbol_rate()
132 stv0299_writereg(fe, 0x14, bclk); in lgtdqcs001f_set_symbol_rate()
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| /linux-6.12.1/include/sound/sof/ |
| D | dai.h | 35 #define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
36 #define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
37 #define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
39 #define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
40 #define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
41 #define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
42 #define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
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| D | dai-intel.h | 45 /* bclk keep active */
49 /* bclk idle */
53 /* bclk early start */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
88 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
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| D | dai-imx.h | 24 uint32_t bclk_rate; /* BCLK frequency in Hz */
45 uint32_t bclk_rate; /* BCLK frequency in Hz */
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| /linux-6.12.1/sound/soc/amd/vangogh/ |
| D | acp5x-mach.c | 171 int ret, bclk; in acp5x_nau8821_hw_params() local
180 bclk = snd_soc_params_to_bclk(params); in acp5x_nau8821_hw_params()
181 if (bclk < 0) { in acp5x_nau8821_hw_params()
182 dev_err(dai->dev, "Fail to get BCLK rate: %d\n", bclk); in acp5x_nau8821_hw_params()
183 return bclk; in acp5x_nau8821_hw_params()
186 ret = snd_soc_dai_set_pll(dai, 0, 0, bclk, params_rate(params) * 256); in acp5x_nau8821_hw_params()
219 unsigned int bclk, rate = params_rate(params); in acp5x_cs35l41_hw_params() local
225 bclk = 1536000; in acp5x_cs35l41_hw_params()
228 bclk = 0; in acp5x_cs35l41_hw_params()
235 if (!bclk) { in acp5x_cs35l41_hw_params()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | imx-audio-card.yaml | 66 fsl,mclk-equal-bclk:
67 description: Indicates mclk can be equal to bclk, especially for sai interface
89 fsl,mclk-equal-bclk;
109 fsl,mclk-equal-bclk;
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| D | tas2552.txt | 18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
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| /linux-6.12.1/drivers/staging/greybus/ |
| D | audio_apbridgea.h | 13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
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| /linux-6.12.1/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8998.c | 127 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
130 int digclk_divsel = bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; in pll_get_integloop_gain()
158 static int pll_get_post_div(struct hdmi_8998_post_divider *pd, u64 bclk) in pll_get_post_div() argument
185 u64 freq = div_u64(bclk, (1 << half_rate_mode)); in pll_get_post_div()
287 u64 bclk; in pll_calculate() local
301 bclk = ((u64)pix_clk) * 10; in pll_calculate()
303 ret = pll_get_post_div(&pd, bclk); in pll_calculate()
321 integloop_gain = pll_get_integloop_gain(frac_start, bclk, in pll_calculate()
330 if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
351 cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x5 : 0x4; in pll_calculate()
[all …]
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| D | hdmi_phy_8996.c | 128 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
131 int digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; in pll_get_integloop_gain()
166 static int pll_get_post_div(struct hdmi_8996_post_divider *pd, u64 bclk) in pll_get_post_div() argument
185 vco = bclk >> half_rate_mode; in pll_get_post_div()
222 u64 bclk; in pll_calculate() local
237 bclk = ((u64)pix_clk) * 10; in pll_calculate()
239 if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
244 ret = pll_get_post_div(&pd, bclk); in pll_calculate()
262 integloop_gain = pll_get_integloop_gain(frac_start, bclk, in pll_calculate()
285 if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
[all …]
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| /linux-6.12.1/sound/soc/codecs/ |
| D | wm9081.c | 151 int bclk; member
658 * gives us a suitable DAC configuration, plus BCLK. in configure_clock()
664 if (wm9081->master && wm9081->bclk) { in configure_clock()
665 /* Make sure we can generate CLK_SYS and BCLK in configure_clock()
671 if (target >= wm9081->bclk && in configure_clock()
1017 /* If TDM is set up then that fixes our BCLK. */ in wm9081_hw_params()
1021 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots; in wm9081_hw_params()
1023 /* Otherwise work out a BCLK from the sample size */ in wm9081_hw_params()
1024 wm9081->bclk = 2 * wm9081->fs; in wm9081_hw_params()
1028 wm9081->bclk *= 16; in wm9081_hw_params()
[all …]
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| D | wm8960.c | 142 int bclk; member
626 * - 10 * bclk = sysclk / bclk_divs
632 * @bclk_idx: bclk_divs index for found bclk
636 * >=0, in case we could derive bclk and lrclk from sysclk using
643 int sysclk, bclk, lrclk; in wm8960_configure_sysclk() local
650 bclk = wm8960->bclk; in wm8960_configure_sysclk()
662 diff = sysclk - bclk * bclk_divs[k] / 10; in wm8960_configure_sysclk()
684 * - 10 * sysclk = bclk * bclk_divs
686 * If we cannot find an exact match for (sysclk, lrclk, bclk)
687 * triplet, we relax the bclk such that bclk is chosen as the
[all …]
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| D | da7219.c | 802 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_dai_event() local
811 if (bclk) { in da7219_dai_event()
812 ret = clk_prepare_enable(bclk); in da7219_dai_event()
858 if (bclk) in da7219_dai_event()
859 clk_disable_unprepare(bclk); in da7219_dai_event()
1427 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_set_dai_tdm_slot() local
1472 if (bclk) { in da7219_set_dai_tdm_slot()
1475 ret = clk_set_rate(bclk, bclk_rate); in da7219_set_dai_tdm_slot()
1478 "Failed to set TDM BCLK rate %lu: %d\n", in da7219_set_dai_tdm_slot()
1563 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_hw_params() local
[all …]
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| /linux-6.12.1/sound/soc/atmel/ |
| D | atmel_ssc_dai.h | 29 #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */
30 #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */
31 #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */
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| /linux-6.12.1/tools/power/cpupower/utils/ |
| D | cpufreq-info.c | 172 double bclk; in get_boost_mode_x86() local
178 bclk = 100.00; in get_boost_mode_x86()
180 bclk = 133.33; in get_boost_mode_x86()
182 dprint (" Ratio: 0x%llx - bclk: %f\n", in get_boost_mode_x86()
183 intel_turbo_ratio, bclk); in get_boost_mode_x86()
188 ratio * bclk); in get_boost_mode_x86()
193 ratio * bclk); in get_boost_mode_x86()
198 ratio * bclk); in get_boost_mode_x86()
203 ratio * bclk); in get_boost_mode_x86()
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| /linux-6.12.1/drivers/iommu/ |
| D | mtk_iommu_v1.c | 100 struct clk *bclk; member
538 ret = clk_prepare_enable(data->bclk); in mtk_iommu_v1_hw_init()
540 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_v1_hw_init()
566 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_hw_init()
634 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_v1_probe()
635 if (IS_ERR(data->bclk)) in mtk_iommu_v1_probe()
636 return PTR_ERR(data->bclk); in mtk_iommu_v1_probe()
696 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_probe()
707 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_remove()
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| /linux-6.12.1/sound/hda/ |
| D | hdac_i915.c | 21 * snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW
24 * Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
26 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
27 * BCLK = CDCLK * M / N
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| /linux-6.12.1/drivers/iio/adc/ |
| D | stm32-adc-core.c | 91 * @bclk: bus clock common for all ADCs, depends on part used
109 struct clk *bclk; member
217 if (!priv->bclk) { in stm32h7_adc_clk_sel()
264 rate = clk_get_rate(priv->bclk); in stm32h7_adc_clk_sel()
270 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); in stm32h7_adc_clk_sel()
559 ret = clk_prepare_enable(priv->bclk); in stm32_adc_core_hw_start()
576 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_start()
595 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_stop()
748 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); in stm32_adc_probe()
749 if (IS_ERR(priv->bclk)) in stm32_adc_probe()
[all …]
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| /linux-6.12.1/sound/soc/ |
| D | soc-utils-test.c | 19 u32 bclk; member
21 /* rate fmt channels tdm_width tdm_slots slot_multiple bclk */
156 tdm_params_to_bclk_cases[i].bclk); in test_tdm_params_to_bclk()
169 tdm_params_to_bclk_cases[i].bclk); in test_tdm_params_to_bclk()
214 tdm_params_to_bclk_cases[i].bclk); in test_snd_soc_params_to_bclk()
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