127 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,  in pll_get_integloop_gain()  argument
130 	int digclk_divsel = bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2;  in pll_get_integloop_gain()
158 static int pll_get_post_div(struct hdmi_8998_post_divider *pd, u64 bclk)  in pll_get_post_div()  argument
185 			u64 freq = div_u64(bclk, (1 << half_rate_mode));  in pll_get_post_div()
287 	u64 bclk;  in pll_calculate()  local
301 	bclk = ((u64)pix_clk) * 10;  in pll_calculate()
303 	ret = pll_get_post_div(&pd, bclk);  in pll_calculate()
321 	integloop_gain = pll_get_integloop_gain(frac_start, bclk,  in pll_calculate()
330 	if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD)  in pll_calculate()
351 	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x5 : 0x4;  in pll_calculate()
356 	if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) {  in pll_calculate()
377 	} else if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) {  in pll_calculate()
398 	} else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) {  in pll_calculate()