Lines Matching full:bclk
151 int bclk; member
658 * gives us a suitable DAC configuration, plus BCLK. in configure_clock()
664 if (wm9081->master && wm9081->bclk) { in configure_clock()
665 /* Make sure we can generate CLK_SYS and BCLK in configure_clock()
671 if (target >= wm9081->bclk && in configure_clock()
1017 /* If TDM is set up then that fixes our BCLK. */ in wm9081_hw_params()
1021 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots; in wm9081_hw_params()
1023 /* Otherwise work out a BCLK from the sample size */ in wm9081_hw_params()
1024 wm9081->bclk = 2 * wm9081->fs; in wm9081_hw_params()
1028 wm9081->bclk *= 16; in wm9081_hw_params()
1031 wm9081->bclk *= 20; in wm9081_hw_params()
1035 wm9081->bclk *= 24; in wm9081_hw_params()
1039 wm9081->bclk *= 32; in wm9081_hw_params()
1047 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk); in wm9081_hw_params()
1091 - wm9081->bclk; in wm9081_hw_params()
1099 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div; in wm9081_hw_params()
1100 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", in wm9081_hw_params()
1101 bclk_divs[best].div, wm9081->bclk); in wm9081_hw_params()
1104 /* LRCLK is a simple fraction of BCLK */ in wm9081_hw_params()
1105 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs); in wm9081_hw_params()
1106 aif4 |= wm9081->bclk / wm9081->fs; in wm9081_hw_params()