| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ring.c | 40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
55 * @type: ring type for which to return the limit.
73 * amdgpu_ring_alloc - allocate space on the ring buffer
75 * @ring: amdgpu_ring structure holding ring information
76 * @ndw: number of dwords to allocate in the ring buffer
78 * Allocate @ndw dwords in the ring buffer (all asics).
81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) in amdgpu_ring_alloc() argument
[all …]
|
| D | amdgpu_ih.c | 24 #include <linux/dma-mapping.h>
30 * amdgpu_ih_ring_init - initialize the IH state
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
38 * for the IH ring buffer.
47 /* Align ring size */ in amdgpu_ih_ring_init()
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
[all …]
|
| D | sdma_v4_0.c | 446 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
448 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
450 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
452 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
453 case 4: in sdma_v4_0_get_reg_offset()
454 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
456 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
458 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
460 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
478 case 4: in sdma_v4_0_seq_to_irq_id()
[all …]
|
| D | jpeg_v4_0_3.c | 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
65 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)); in jpeg_v4_0_3_normalizn_reqd()
69 * jpeg_v4_0_3_early_init - set function pointers
73 * Set ring and irq function pointers
79 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; in jpeg_v4_0_3_early_init()
89 * jpeg_v4_0_3_sw_init - sw init for JPEG block
98 struct amdgpu_ring *ring; in jpeg_v4_0_3_sw_init() local
101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
104 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v4_0_3_sw_init()
117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
[all …]
|
| D | amdgpu_vpe.c | 34 /* VPE CSA resides in the 4th page of CSA */
40 #define VPE_MAX_DPM_LEVEL 4
85 remainder -= arg2_value; in vpe_u1_8_from_fraction()
87 } while (--i != 0); in vpe_u1_8_from_fraction()
114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),
123 struct amdgpu_device *adev = vpe->ring.adev; in amdgpu_vpe_configure_dpm()
126 if (adev->pm.dpm_enabled) { in amdgpu_vpe_configure_dpm()
135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); in amdgpu_vpe_configure_dpm()
137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); in amdgpu_vpe_configure_dpm()
141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); in amdgpu_vpe_configure_dpm()
[all …]
|
| D | sdma_v4_4_2.c | 114 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); in sdma_v4_4_2_get_reg_offset()
129 return -EINVAL; in sdma_v4_4_2_seq_to_irq_id()
141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
151 return -EINVAL; in sdma_v4_4_2_irq_id_to_seq()
161 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); in sdma_v4_4_2_inst_init_golden_registers()
170 4); in sdma_v4_4_2_inst_init_golden_registers()
178 * sdma_v4_4_2_init_microcode - load ucode images from disk
190 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
[all …]
|
| D | gfx_v9_0.c | 379 /* TCC (5 sub-ranges)*/
416 /* TCC range 4*/
442 /* EA (3 sub-ranges)*/
479 /* UTC ATC L2 4KB cache*/
854 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
855 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
856 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
857 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
858 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
859 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
[all …]
|
| D | si_dma.c | 41 static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring) in si_dma_ring_get_rptr() argument
43 return *ring->rptr_cpu_addr; in si_dma_ring_get_rptr()
46 static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring) in si_dma_ring_get_wptr() argument
48 struct amdgpu_device *adev = ring->adev; in si_dma_ring_get_wptr()
49 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_get_wptr()
54 static void si_dma_ring_set_wptr(struct amdgpu_ring *ring) in si_dma_ring_set_wptr() argument
56 struct amdgpu_device *adev = ring->adev; in si_dma_ring_set_wptr()
57 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_set_wptr()
59 WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); in si_dma_ring_set_wptr()
62 static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, in si_dma_ring_emit_ib() argument
[all …]
|
| D | gfx_v9_4_3.c | 173 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v9_4_3_kiq_set_resources()
177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_4_3_kiq_set_resources()
195 struct amdgpu_ring *ring) in gfx_v9_4_3_kiq_map_queues() argument
197 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v9_4_3_kiq_map_queues()
198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); in gfx_v9_4_3_kiq_map_queues()
199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_4_3_kiq_map_queues()
200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx_v9_4_3_kiq_map_queues()
207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | in gfx_v9_4_3_kiq_map_queues()
208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | in gfx_v9_4_3_kiq_map_queues()
209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | in gfx_v9_4_3_kiq_map_queues()
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/broadcom/ |
| D | bgmac.c | 33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); in bgmac_wait_value()
41 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) in bgmac_dma_tx_reset() argument
46 if (!ring->mmio_base) in bgmac_dma_tx_reset()
49 /* Suspend DMA TX ring first. in bgmac_dma_tx_reset()
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, in bgmac_dma_tx_reset()
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", in bgmac_dma_tx_reset()
68 ring->mmio_base, val); in bgmac_dma_tx_reset()
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); in bgmac_dma_tx_reset()
73 ring->mmio_base + BGMAC_DMA_TX_STATUS, in bgmac_dma_tx_reset()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | r600_dma.c | 34 * to the 3D engine (ring buffer, IBs, etc.), but the
43 * r600_dma_get_rptr - get the current read pointer
46 * @ring: radeon ring pointer
51 struct radeon_ring *ring) in r600_dma_get_rptr() argument
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
67 * @ring: radeon ring pointer
72 struct radeon_ring *ring) in r600_dma_get_wptr() argument
78 * r600_dma_set_wptr - commit the write pointer
[all …]
|
| D | radeon_ring.c | 39 * Most engines on the GPU are fed via ring buffers. Ring
45 * pointers are equal, the ring is idle. When the host
46 * writes commands to the ring buffer, it increments the
50 static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
53 * radeon_ring_supports_scratch_reg - check if the ring supports
57 * @ring: radeon_ring structure holding ring information
59 * Check if a specific ring supports writing to scratch registers (all asics).
60 * Returns true if the ring supports writing to scratch regs, false if not.
63 struct radeon_ring *ring) in radeon_ring_supports_scratch_reg() argument
65 switch (ring->idx) { in radeon_ring_supports_scratch_reg()
[all …]
|
| D | evergreen_dma.c | 31 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
36 * Add a DMA fence packet to the ring to write
38 * an interrupt if needed (evergreen-SI).
43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit() local
44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
46 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
51 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
[all …]
|
| D | cik_sdma.c | 38 * sDMA - System DMA
42 * and each one supports 1 ring buffer used for gfx
46 * (ring buffer, IBs, etc.), but sDMA has it's own
55 * cik_sdma_get_rptr - get the current read pointer
58 * @ring: radeon ring pointer
63 struct radeon_ring *ring) in cik_sdma_get_rptr() argument
67 if (rdev->wb.enabled) { in cik_sdma_get_rptr()
68 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
82 * cik_sdma_get_wptr - get the current write pointer
[all …]
|
| D | ni.c | 52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
439 switch (rdev->family) { in ni_init_golden_registers()
449 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
450 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
451 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
452 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
453 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
[all …]
|
| D | vce_v1_0.c | 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
47 uint32_t nonce[4];
48 uint32_t sigval[4];
53 * vce_v1_0_get_rptr - get read pointer
56 * @ring: radeon_ring pointer
61 struct radeon_ring *ring) in vce_v1_0_get_rptr() argument
63 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_rptr()
70 * vce_v1_0_get_wptr - get write pointer
73 * @ring: radeon_ring pointer
78 struct radeon_ring *ring) in vce_v1_0_get_wptr() argument
[all …]
|
| D | ni_dma.c | 35 * to the 3D engine (ring buffer, IBs, etc.), but the
45 * cayman_dma_get_rptr - get the current read pointer
48 * @ring: radeon ring pointer
53 struct radeon_ring *ring) in cayman_dma_get_rptr() argument
57 if (rdev->wb.enabled) { in cayman_dma_get_rptr()
58 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_dma_get_rptr()
60 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cayman_dma_get_rptr()
72 * cayman_dma_get_wptr - get the current write pointer
75 * @ring: radeon ring pointer
80 struct radeon_ring *ring) in cayman_dma_get_wptr() argument
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/apm/xgene/ |
| D | xgene_enet_ring2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
30 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
[all …]
|
| /linux-6.12.1/drivers/soc/ti/ |
| D | k3-ringacc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TI K3 NAVSS Ring Accelerator subsystem driver
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/dma-mapping.h>
14 #include <linux/dma/ti-cppi5.h>
15 #include <linux/soc/ti/k3-ringacc.h>
28 * struct k3_ring_rt_regs - The RA realtime Control/Status Registers region
31 * @db: Ring Doorbell Register
33 * @occ: Ring Occupancy Register
34 * @indx: Ring Current Index Register
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-io.json | 13 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
14 "ScaleUnit": "4Bytes",
29 …"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) t…
30 "ScaleUnit": "4Bytes",
66 "Counter": "4",
145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
152 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
205 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
212 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
253 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | uncore-io.json | 34 "Counter": "4",
114 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
121 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
174 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
181 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
222 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
229 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
234 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
240 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
289 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/freescale/ |
| D | gianfar.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
67 #define DRV_NAME "gfar-enet"
87 #define DEFAULT_LFC_PTVVAL 4
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
281 /* weighted round-robin scheduling (WRRS) */
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/hisilicon/hns3/ |
| D | hns3_enet.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
70 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
87 #define HNS3_RXD_L3ID_S 4
112 #define HNS3_RXD_OL3ID_S 4
121 #define HNS3_RXD_PTYPE_S 4
122 #define HNS3_RXD_PTYPE_M GENMASK(11, 4)
126 #define HNS3_RXD_VLD_B 4
144 #define HNS3_TXD_L3CS_B 4
163 #define HNS3_TXD_TUNTYPE_S 4
[all …]
|
| /linux-6.12.1/drivers/dma/ |
| D | fsl_raid.h | 13 * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
44 #define FSL_RE_MAX_CHANS 4
67 #define FSL_RE_RING_SIZE_MASK (FSL_RE_RING_SIZE - 1)
69 #define FSL_RE_ADDR_BIT_SHIFT 4
70 #define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1)
114 u8 rsvd1[4];
116 u8 rsvd2[4];
118 u8 rsvd3[4];
138 u8 rsvd1[4];
140 u8 rsvd2[4];
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_rcb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
31 *hns_rcb_wait_fbd_clean - clean fbd
32 *@qs: ring struct pointer array
57 dev_err(qs[i]->handle->owner_dev, in hns_rcb_wait_fbd_clean()
66 tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL); in hns_rcb_wait_tx_ring_clean()
69 head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD); in hns_rcb_wait_tx_ring_clean()
77 dev_err(qs->dev->dev, "rcb wait timeout, head not equal to tail.\n"); in hns_rcb_wait_tx_ring_clean()
78 return -EBUSY; in hns_rcb_wait_tx_ring_clean()
85 *hns_rcb_reset_ring_hw - ring reset
[all …]
|