Lines Matching +full:4 +full:- +full:ring
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
47 uint32_t nonce[4];
48 uint32_t sigval[4];
53 * vce_v1_0_get_rptr - get read pointer
56 * @ring: radeon_ring pointer
61 struct radeon_ring *ring) in vce_v1_0_get_rptr() argument
63 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_rptr()
70 * vce_v1_0_get_wptr - get write pointer
73 * @ring: radeon_ring pointer
78 struct radeon_ring *ring) in vce_v1_0_get_wptr() argument
80 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_wptr()
87 * vce_v1_0_set_wptr - set write pointer
90 * @ring: radeon_ring pointer
95 struct radeon_ring *ring) in vce_v1_0_set_wptr() argument
97 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_set_wptr()
98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
107 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) { in vce_v1_0_enable_mgcg()
160 struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data; in vce_v1_0_load_fw()
164 switch (rdev->family) { in vce_v1_0_load_fw()
178 return -EINVAL; in vce_v1_0_load_fw()
181 for (i = 0; i < le32_to_cpu(sign->num); ++i) { in vce_v1_0_load_fw()
182 if (le32_to_cpu(sign->val[i].chip_id) == chip_id) in vce_v1_0_load_fw()
186 if (i == le32_to_cpu(sign->num)) in vce_v1_0_load_fw()
187 return -EINVAL; in vce_v1_0_load_fw()
189 data += (256 - 64) / 4; in vce_v1_0_load_fw()
190 data[0] = sign->val[i].nonce[0]; in vce_v1_0_load_fw()
191 data[1] = sign->val[i].nonce[1]; in vce_v1_0_load_fw()
192 data[2] = sign->val[i].nonce[2]; in vce_v1_0_load_fw()
193 data[3] = sign->val[i].nonce[3]; in vce_v1_0_load_fw()
194 data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64); in vce_v1_0_load_fw()
197 memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign)); in vce_v1_0_load_fw()
199 data += (le32_to_cpu(sign->len) + 64) / 4; in vce_v1_0_load_fw()
200 data[0] = sign->val[i].sigval[0]; in vce_v1_0_load_fw()
201 data[1] = sign->val[i].sigval[1]; in vce_v1_0_load_fw()
202 data[2] = sign->val[i].sigval[2]; in vce_v1_0_load_fw()
203 data[3] = sign->val[i].sigval[3]; in vce_v1_0_load_fw()
205 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); in vce_v1_0_load_fw()
212 WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->size); in vce_v1_0_bo_size()
218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
254 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); in vce_v1_0_resume()
263 return -ETIMEDOUT; in vce_v1_0_resume()
266 return -EINVAL; in vce_v1_0_resume()
275 return -ETIMEDOUT; in vce_v1_0_resume()
283 * vce_v1_0_start - start VCE block
291 struct radeon_ring *ring; in vce_v1_0_start() local
297 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in vce_v1_0_start()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
302 WREG32(VCE_RB_SIZE, ring->ring_size / 4); in vce_v1_0_start()
304 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
309 WREG32(VCE_RB_SIZE2, ring->ring_size / 4); in vce_v1_0_start()
342 r = -1; in vce_v1_0_start()
358 struct radeon_ring *ring; in vce_v1_0_init() local
365 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in vce_v1_0_init()
366 ring->ready = true; in vce_v1_0_init()
367 r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring); in vce_v1_0_init()
369 ring->ready = false; in vce_v1_0_init()
373 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in vce_v1_0_init()
374 ring->ready = true; in vce_v1_0_init()
375 r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring); in vce_v1_0_init()
377 ring->ready = false; in vce_v1_0_init()