Lines Matching +full:4 +full:- +full:ring
24 #include <linux/dma-mapping.h>
30 * amdgpu_ih_ring_init - initialize the IH state
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
38 * for the IH ring buffer.
47 /* Align ring size */ in amdgpu_ih_ring_init()
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
52 ih->rptr = 0; in amdgpu_ih_ring_init()
53 ih->use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
58 if (ih->ring) in amdgpu_ih_ring_init()
62 * add them to the end of the ring allocation. in amdgpu_ih_ring_init()
64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, in amdgpu_ih_ring_init()
66 if (ih->ring == NULL) in amdgpu_ih_ring_init()
67 return -ENOMEM; in amdgpu_ih_ring_init()
69 ih->gpu_addr = dma_addr; in amdgpu_ih_ring_init()
70 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; in amdgpu_ih_ring_init()
72 ih->rptr_addr = dma_addr + ih->ring_size + 4; in amdgpu_ih_ring_init()
73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; in amdgpu_ih_ring_init()
87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, in amdgpu_ih_ring_init()
89 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init()
90 (void **)&ih->ring); in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init()
100 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; in amdgpu_ih_ring_init()
103 init_waitqueue_head(&ih->wait_process); in amdgpu_ih_ring_init()
108 * amdgpu_ih_ring_fini - tear down the IH state
111 * @ih: ih ring to tear down
114 * used for the IH ring buffer.
119 if (!ih->ring) in amdgpu_ih_ring_fini()
122 if (ih->use_bus_addr) { in amdgpu_ih_ring_fini()
125 * add them to the end of the ring allocation. in amdgpu_ih_ring_fini()
127 dma_free_coherent(adev->dev, ih->ring_size + 8, in amdgpu_ih_ring_fini()
128 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini()
129 ih->ring = NULL; in amdgpu_ih_ring_fini()
131 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini()
132 (void **)&ih->ring); in amdgpu_ih_ring_fini()
133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
139 * amdgpu_ih_ring_write - write IV to the ring buffer
142 * @ih: ih ring to write to
146 * Writes an IV to the ring buffer using the CPU and increment the wptr.
147 * Used for testing and delegating IVs to a software ring.
152 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write()
156 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write()
159 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write()
162 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
164 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write()
165 } else if (adev->irq.retry_cam_enabled) { in amdgpu_ih_ring_write()
166 dev_warn_once(adev->dev, "IH soft ring buffer overflow 0x%X, 0x%X\n", in amdgpu_ih_ring_write()
167 wptr, ih->rptr); in amdgpu_ih_ring_write()
172 * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to checkpoint
175 * @ih: ih ring to process
177 * Used to ensure ring has processed IVs up to the checkpoint write pointer.
186 if (!ih->enabled || adev->shutdown) in amdgpu_ih_wait_on_checkpoint_process_ts()
187 return -ENODEV; in amdgpu_ih_wait_on_checkpoint_process_ts()
190 /* Order wptr with ring data. */ in amdgpu_ih_wait_on_checkpoint_process_ts()
192 checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1); in amdgpu_ih_wait_on_checkpoint_process_ts()
194 return wait_event_interruptible_timeout(ih->wait_process, in amdgpu_ih_wait_on_checkpoint_process_ts()
195 amdgpu_ih_ts_after(checkpoint_ts, ih->processed_timestamp) || in amdgpu_ih_wait_on_checkpoint_process_ts()
196 ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout); in amdgpu_ih_wait_on_checkpoint_process_ts()
200 * amdgpu_ih_process - interrupt handler
203 * @ih: ih ring to process
205 * Interrupt hander (VI), walk the IH ring.
213 if (!ih->enabled || adev->shutdown) in amdgpu_ih_process()
220 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
222 /* Order reading of wptr vs. reading of IH ring data */ in amdgpu_ih_process()
225 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
227 ih->rptr &= ih->ptr_mask; in amdgpu_ih_process()
231 wake_up_all(&ih->wait_process); in amdgpu_ih_process()
235 if (wptr != ih->rptr) in amdgpu_ih_process()
242 * amdgpu_ih_decode_iv_helper - decode an interrupt vector
245 * @ih: ih ring to process
257 u32 ring_index = ih->rptr >> 2; in amdgpu_ih_decode_iv_helper()
260 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in amdgpu_ih_decode_iv_helper()
261 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in amdgpu_ih_decode_iv_helper()
262 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in amdgpu_ih_decode_iv_helper()
263 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in amdgpu_ih_decode_iv_helper()
264 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); in amdgpu_ih_decode_iv_helper()
265 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); in amdgpu_ih_decode_iv_helper()
266 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); in amdgpu_ih_decode_iv_helper()
267 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); in amdgpu_ih_decode_iv_helper()
269 entry->client_id = dw[0] & 0xff; in amdgpu_ih_decode_iv_helper()
270 entry->src_id = (dw[0] >> 8) & 0xff; in amdgpu_ih_decode_iv_helper()
271 entry->ring_id = (dw[0] >> 16) & 0xff; in amdgpu_ih_decode_iv_helper()
272 entry->vmid = (dw[0] >> 24) & 0xf; in amdgpu_ih_decode_iv_helper()
273 entry->vmid_src = (dw[0] >> 31); in amdgpu_ih_decode_iv_helper()
274 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); in amdgpu_ih_decode_iv_helper()
275 entry->timestamp_src = dw[2] >> 31; in amdgpu_ih_decode_iv_helper()
276 entry->pasid = dw[3] & 0xffff; in amdgpu_ih_decode_iv_helper()
277 entry->node_id = (dw[3] >> 16) & 0xff; in amdgpu_ih_decode_iv_helper()
278 entry->src_data[0] = dw[4]; in amdgpu_ih_decode_iv_helper()
279 entry->src_data[1] = dw[5]; in amdgpu_ih_decode_iv_helper()
280 entry->src_data[2] = dw[6]; in amdgpu_ih_decode_iv_helper()
281 entry->src_data[3] = dw[7]; in amdgpu_ih_decode_iv_helper()
284 ih->rptr += 32; in amdgpu_ih_decode_iv_helper()
295 ring_index = (rptr & ih->ptr_mask) >> 2; in amdgpu_ih_decode_iv_ts_helper()
297 dw1 = le32_to_cpu(ih->ring[ring_index + 1]); in amdgpu_ih_decode_iv_ts_helper()
298 dw2 = le32_to_cpu(ih->ring[ring_index + 2]); in amdgpu_ih_decode_iv_ts_helper()