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/linux-6.12.1/arch/riscv/net/
Dbpf_jit.h35 RV_REG_GP = 3, /* Global pointer */
241 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
245 (rd << 7) | opcode; in rv_r_insn()
248 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
250 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
271 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) in rv_u_insn() argument
273 return (imm31_12 << 12) | (rd << 7) | opcode; in rv_u_insn()
276 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode) in rv_j_insn() argument
283 return (imm << 12) | (rd << 7) | opcode; in rv_j_insn()
287 u8 funct3, u8 rd, u8 opcode) in rv_amo_insn() argument
[all …]
/linux-6.12.1/arch/x86/crypto/
Dserpent-sse2-i586-asm_32.S30 #define RD %xmm3 macro
49 get_key(i, 3, x4); \
59 pslld $3, x2; \
60 psrld $(32 - 3), x4; \
68 pslld $3, x4; \
84 get_key(i, 3, RT0); \
124 pslld $3, x4; \
133 psrld $3, x2; \
134 pslld $(32 - 3), x4; \
472 movdqu (3*4*4)(in), x3; \
[all …]
Dserpent-sse2-x86_64-asm_64.S381 get_key(i, 3, RK3); \
398 pslld $3, x2 ## 1; \
399 psrld $(32 - 3), x4 ## 1; \
408 pslld $3, x2 ## 2; \
409 psrld $(32 - 3), x4 ## 2; \
417 pslld $3, x4 ## 1; \
427 pslld $3, x4 ## 2; \
431 get_key(i, 3, RK3); \
528 pslld $3, x4 ## 1; \
537 pslld $3, x4 ## 2; \
[all …]
Dserpent-avx-x86_64-asm_64.S20 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
374 get_key(i, 3, RK3); \
389 vpslld $3, x2 ## 1, x4 ## 1; \
390 vpsrld $(32 - 3), x2 ## 1, x2 ## 1; \
397 vpslld $3, x2 ## 2, x4 ## 2; \
398 vpsrld $(32 - 3), x2 ## 2, x2 ## 2; \
404 vpslld $3, x0 ## 1, x4 ## 1; \
411 vpslld $3, x0 ## 2, x4 ## 2; \
414 get_key(i, 3, RK3); \
495 vpslld $3, x0 ## 1, x4 ## 1; \
[all …]
Dserpent-avx2-asm_64.S21 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
374 get_key(i, 3, RK3); \
389 vpslld $3, x2 ## 1, x4 ## 1; \
390 vpsrld $(32 - 3), x2 ## 1, x2 ## 1; \
397 vpslld $3, x2 ## 2, x4 ## 2; \
398 vpsrld $(32 - 3), x2 ## 2, x2 ## 2; \
404 vpslld $3, x0 ## 1, x4 ## 1; \
411 vpslld $3, x0 ## 2, x4 ## 2; \
414 get_key(i, 3, RK3); \
495 vpslld $3, x0 ## 1, x4 ## 1; \
[all …]
/linux-6.12.1/arch/loongarch/kernel/
Dinst.c16 unsigned int rd = insn.reg1i20_format.rd; in simu_pc() local
19 if (pc & 3) { in simu_pc()
26 regs->regs[rd] = pc + sign_extend64(imm << 2, 21); in simu_pc()
29 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
32 regs->regs[rd] = pc + sign_extend64(imm << 18, 37); in simu_pc()
35 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
36 regs->regs[rd] &= ~((1 << 12) - 1); in simu_pc()
48 unsigned int imm, imm_l, imm_h, rd, rj; in simu_branch() local
51 if (pc & 3) { in simu_branch()
88 rd = insn.reg2i16_format.rd; in simu_branch()
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/linux-6.12.1/arch/arm64/crypto/
Dsm3-neon-core.S28 #define STACK_W_SIZE (32 * 2 * 3)
44 #define rd w6 macro
132 IOP(3, iop_param); \
172 (STACK_W + ((((round) / 3) - 4) % 2) * 64 + (offs) + ((widx) * 4))
242 /* Message scheduling. Note: 3 words per vector register.
259 /* w[i - 3] == w5 */ \
290 /* Load (w[i - 3]) => XTMP2 */ \
354 .align 3
357 ldp rc, rd, [RSTATE, #8]
375 LOAD_W_VEC_1(3, 0)
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Dsm3-ce-core.S12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
16 .macro sm3partw1, rd, rn, rm
17 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
20 .macro sm3partw2, rd, rn, rm
21 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
24 .macro sm3ss1, rd, rn, rm, ra
25 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .macro sm3tt1a, rd, rn, rm, imm2
29 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
32 .macro sm3tt1b, rd, rn, rm, imm2
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/linux-6.12.1/include/linux/ceph/
Drados.h31 #define CEPH_MAXSNAP ((__u64)(-3)) /* largest valid snapid */
44 #define CEPH_OBJECT_LAYOUT_HASHINO 3
52 #define CEPH_PG_LAYOUT_HYBRID 3
87 #define CEPH_POOL_TYPE_EC 3
130 #define CEPH_OSD_NEW (1<<3) /* osd is new, never marked in */
151 #define CEPH_OSDMAP_PAUSEWR (1<<3) /* pause all writes */
206 f(READ, __CEPH_OSD_OP(RD, DATA, 1), "read") \
207 f(STAT, __CEPH_OSD_OP(RD, DATA, 2), "stat") \
208 f(MAPEXT, __CEPH_OSD_OP(RD, DATA, 3), "mapext") \
211 f(MASKTRUNC, __CEPH_OSD_OP(RD, DATA, 4), "masktrunc") \
[all …]
/linux-6.12.1/arch/arm/lib/
Dio-writesb.S10 .macro outword, rd argument
12 strb \rd, [r0]
13 mov \rd, \rd, lsr #8
14 strb \rd, [r0]
15 mov \rd, \rd, lsr #8
16 strb \rd, [r0]
17 mov \rd, \rd, lsr #8
18 strb \rd, [r0]
20 mov lr, \rd, lsr #24
22 mov lr, \rd, lsr #16
[all …]
Dio-writesw-armv4.S10 .macro outword, rd argument
12 strh \rd, [r0]
13 mov \rd, \rd, lsr #16
14 strh \rd, [r0]
16 mov lr, \rd, lsr #16
18 strh \rd, [r0]
32 ands r3, r1, #3
82 bmi 3f
94 3: movne ip, r3, lsr #8
/linux-6.12.1/arch/arm/mach-tegra/
Dsleep.h51 .macro cpu_to_halt_reg rd, rcpu
53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
60 .macro cpu_to_csr_reg rd, rcpu
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
[all …]
Dsleep-tegra30.S59 #define CLK_RESET_PLLX_MISC3_IDDQ 3
77 #define PLLP_STORE_MASK (1 << 3)
83 .macro emc_device_mask, rd, base
84 ldr \rd, [\base, #EMC_ADR_CFG]
85 tst \rd, #0x1
86 moveq \rd, #(0x1 << 8) @ just 1 device
87 movne \rd, #(0x3 << 8) @ 2 devices
90 .macro emc_timing_update, rd, base
91 mov \rd, #1
92 str \rd, [\base, #EMC_TIMING_CONTROL]
[all …]
/linux-6.12.1/arch/arc/net/
Dbpf_jit_arcv2.c33 * - BPF_REG_{1,2,3,4} are the argument registers and must be mapped to
111 ZZ_8_byte = 3
129 AA_scale = 3 /* in assembly known as "as". */
143 CC_positive = 3, /* if status32.n flag is clear */
268 #define STORE_AA(x) ((x) << 3)
668 /* rd <- rs */
669 static u8 arc_mov_r(u8 *buf, u8 rd, u8 rs) in arc_mov_r() argument
671 const u32 insn = OPC_MOV | OP_B(rd) | OP_C(rs); in arc_mov_r()
679 static u8 arc_mov_i(u8 *buf, u8 rd, s32 imm) in arc_mov_i() argument
681 const u32 insn = OPC_MOV | OP_B(rd) | OP_IMM; in arc_mov_i()
[all …]
/linux-6.12.1/kernel/sched/
Dtopology.c231 pr_info("rd %*pbl: Checking EAS, CPUs do not have asymmetric capacities\n", in sched_is_eas_possible()
240 pr_info("rd %*pbl: Checking EAS, SMT is not supported\n", in sched_is_eas_possible()
248 pr_info("rd %*pbl: Checking EAS: frequency-invariant load tracking not yet supported", in sched_is_eas_possible()
259 pr_info("rd %*pbl: Checking EAS, cpufreq policy not set for CPU: %d", in sched_is_eas_possible()
268 pr_info("rd %*pbl: Checking EAS, schedutil is mandatory\n", in sched_is_eas_possible()
421 * 3. no SMT is detected.
422 * 4. schedutil is driving the frequency of all CPUs of the rd;
430 struct root_domain *rd = cpu_rq(cpu)->rd; in build_perf_domains() local
454 tmp = rd->pd; in build_perf_domains()
455 rcu_assign_pointer(rd->pd, pd); in build_perf_domains()
[all …]
/linux-6.12.1/arch/arm/net/
Dbpf_jit_32.h15 #define ARM_R3 3
51 #define SRTYPE_ROR 3
165 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
167 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
171 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
172 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
173 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
174 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
175 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
176 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
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/linux-6.12.1/arch/arm/mm/
Dalignment.c56 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
182 #define TYPE_DONE 3
204 "3: mov %0, #1\n" \
208 " .align 3\n" \
209 " .long 1b, 3b\n" \
261 "3:\n" \
265 " b 3b\n" \
268 " .align 3\n" \
296 ARM( "3: "ins" %1, [%2], #1\n" ) \
[all …]
/linux-6.12.1/lib/
Dwin_minmax.c12 * The algorithm keeps track of the best, 2nd best & 3rd best min
22 * every new min and overwrites 2nd & 3rd choices. The same property
23 * holds for 2nd & 3rd best.
28 /* As time advances, update the 1st, 2nd, and 3rd choices. */
37 * choice the new val & 3rd choice the new 2nd choice. in minmax_subwin_update()
59 * so take a 3rd choice from the last half of the window in minmax_subwin_update()
66 /* Check if new measurement updates the 1st, 2nd or 3rd choice max. */
84 /* Check if new measurement updates the 1st, 2nd or 3rd choice min. */
/linux-6.12.1/arch/arm/include/asm/
Dassembler.h203 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
208 .macro badr\c, rd, sym
210 adr\c \rd, \sym + 1
212 adr\c \rd, \sym
220 .macro get_thread_info, rd
222 get_current \rd
251 .align 3; \
291 * register 'rd'
293 .macro this_cpu_offset, rd:req
295 ALT_SMP(mrc p15, 0, \rd, c13, c0, 4)
[all …]
/linux-6.12.1/arch/microblaze/kernel/
Dhw_exception_handler.S142 #define BSRLI2(rD, rA) \ argument
143 srl rD, rA; /* << 1 */ \
144 srl rD, rD; /* << 2 */
145 #define BSRLI4(rD, rA) \ argument
146 BSRLI2(rD, rA); \
147 BSRLI2(rD, rD)
148 #define BSRLI10(rD, rA) \ argument
149 srl rD, rA; /* << 1 */ \
150 srl rD, rD; /* << 2 */ \
151 srl rD, rD; /* << 3 */ \
[all …]
/linux-6.12.1/arch/powerpc/lib/
Dsstep.c33 #define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe)) argument
99 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) in branch_taken()
148 ea = (signed short) (instr & ~3); /* sign-extend */ in dsform_ea()
286 up[0] = byterev_8(up[3]); in do_byte_reverse()
287 up[3] = tmp; in do_byte_reverse()
837 i = IS_LE ? 3 - j : j; in emulate_vsx_load()
841 u32 val = reg->w[IS_LE ? 3 : 0]; in emulate_vsx_load()
843 i = IS_LE ? 3 - j : j; in emulate_vsx_load()
936 i = IS_LE ? 3 - j : j; in emulate_vsx_store()
1101 "1: " op " %2,0,%3\n" \
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/
Dmsm_rd.c9 * tail -f /sys/kernel/debug/dri/<minor>/rd > logfile.rd
18 * tail -f /sys/kernel/debug/dri/<minor>/hangrd > logfile.rd
45 MODULE_PARM_DESC(rd_full, "If true, $debugfs/.../rd will snapshot all buffer contents");
97 static void rd_write(struct msm_rd_state *rd, const void *buf, int sz) in rd_write() argument
99 struct circ_buf *fifo = &rd->fifo; in rd_write()
106 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open); in rd_write()
107 if (!rd->open) in rd_write()
114 n = min(sz, circ_space_to_end(&rd->fifo)); in rd_write()
121 wake_up_all(&rd->fifo_event); in rd_write()
125 static void rd_write_section(struct msm_rd_state *rd, in rd_write_section() argument
[all …]
/linux-6.12.1/arch/arm/include/debug/
Dtegra.S84 and \rv, \rv, #3
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
87 cmp \rv, #3 @ so accept either
97 cmp \rv, #3 @ UART 3?
192 .macro senduart, rd, rx
194 strbne \rd, [\rx, #UART_TX << UART_SHIFT]
198 .macro busyuart, rd, rx
201 1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
202 and \rd, \rd, #UART_LSR_THRE
203 teq \rd, #UART_LSR_THRE
[all …]
Domap2plus.S11 /* External port on Zoom2/3 */
63 .macro senduart,rd,rx
64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
66 strb \rd, [\rx] @ send lower byte of rd
67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
68 bic \rd, \rd, #(0xff << 24) @ restore original rd
71 .macro busyuart,rd,rx
72 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
73 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
74 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dsha1-powerpc-asm.S28 #define RB(t) ((((t)+3)%6)+7)
30 #define RD(t) ((((t)+1)%6)+7) macro
40 andc r0,RD(t),RB(t); \
53 andc r0,RD(t),RB(t); \
58 xor r5,W((t)+4-3),W((t)+4-8); \
70 xor r6,r6,RD(t); \
80 xor r6,r6,RD(t); \
82 xor r5,W((t)+4-3),W((t)+4-8); \
92 and r0,RB(t),RD(t); \
96 and r0,RC(t),RD(t); \
[all …]

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