arm/mach-tegra/sleep-tegra30.S

59 #define CLK_RESET_PLLX_MISC3_IDDQ	3
77 #define PLLP_STORE_MASK			(1 << 3)
83 .macro emc_device_mask, rd, base
84 	ldr	\rd, [\base, #EMC_ADR_CFG]
85 	tst	\rd, #0x1
86 	moveq	\rd, #(0x1 << 8)		@ just 1 device
87 	movne	\rd, #(0x3 << 8)		@ 2 devices
90 .macro emc_timing_update, rd, base
91 	mov	\rd, #1
92 	str	\rd, [\base, #EMC_TIMING_CONTROL]
94 	ldr	\rd, [\base, #EMC_EMC_STATUS]
95 	tst	\rd, #(0x1<<23)	@ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
99 .macro test_pll_state, rd, test_mask
100 	ldr	\rd, tegra_pll_state
101 	tst	\rd, #\test_mask
104 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
105 	ldr	\rd, [\r_car_base, #\pll_base]
106 	tst	\rd, #(1 << 30)
107 	ldr	\rd, tegra_pll_state
108 	biceq	\rd, \rd, #\pll_mask
109 	orrne	\rd, \rd, #\pll_mask
111 	str	\rd, [\tmp]
114 .macro store_pllm_pmc_state, rd, tmp, pmc_base
115 	ldr	\rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
116 	tst	\rd, #(1 << 12)
117 	ldr	\rd, tegra_pll_state
118 	biceq	\rd, \rd, #PLLM_PMC_STORE_MASK
119 	orrne	\rd, \rd, #PLLM_PMC_STORE_MASK
121 	str	\rd, [\tmp]
124 .macro pllm_pmc_enable, rd, pmc_base
125 	test_pll_state \rd, PLLM_PMC_STORE_MASK
127 	ldrne	\rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
128 	orrne	\rd, \rd, #(1 << 12)
129 	strne	\rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
132 .macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask
133 	test_pll_state \rd, \test_mask
136 	ldr	\rd, [\r_car_base, #\pll_base]
137 	tst	\rd, #(1 << 30)
138 	orreq	\rd, \rd, #(1 << 30)
139 	streq	\rd, [\r_car_base, #\pll_base]
142 	ldr	\rd, [\r_car_base, #\pll_misc]
143 	bic	\rd, \rd, #(1 << 18)
144 	str	\rd, [\r_car_base, #\pll_misc]
145 	ldr	\rd, [\r_car_base, #\pll_misc]
146 	ldr	\rd, [\r_car_base, #\pll_misc]
147 	orr	\rd, \rd, #(1 << 18)
148 	str	\rd, [\r_car_base, #\pll_misc]
153 .macro pll_locked, rd, r_car_base, pll_base, test_mask
154 	test_pll_state \rd, \test_mask
157 	ldr	\rd, [\r_car_base, #\pll_base]
158 	tst	\rd, #(1 << 27)
163 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
164 	ldr	\rd, [\car, #\iddq]
165 	bic	\rd, \rd, #(1<<\iddq_bit)
166 	str	\rd, [\car, #\iddq]
169 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
170 	ldr	\rd, [\car, #\iddq]
171 	orr	\rd, \rd, #(1<<\iddq_bit)
172 	str	\rd, [\car, #\iddq]
525 	and	r2, r2,	#3		@ check DRAM_TYPE
847 	mov	r1, #3