142 	#define BSRLI2(rD, rA)				\  argument
143 		srl rD, rA;		/* << 1 */	\
144 		srl rD, rD;		/* << 2 */
145 	#define BSRLI4(rD, rA)		\  argument
146 		BSRLI2(rD, rA);		\
147 		BSRLI2(rD, rD)
148 	#define BSRLI10(rD, rA)				\  argument
149 		srl rD, rA;		/* << 1 */	\
150 		srl rD, rD;		/* << 2 */	\
151 		srl rD, rD;		/* << 3 */	\
152 		srl rD, rD;		/* << 4 */	\
153 		srl rD, rD;		/* << 5 */	\
154 		srl rD, rD;		/* << 6 */	\
155 		srl rD, rD;		/* << 7 */	\
156 		srl rD, rD;		/* << 8 */	\
157 		srl rD, rD;		/* << 9 */	\
158 		srl rD, rD		/* << 10 */
159 	#define BSRLI20(rD, rA)		\  argument
160 		BSRLI10(rD, rA);	\
161 		BSRLI10(rD, rD)
163 	.macro	bsrli, rD, rA, IMM
165 		BSRLI2(\rD, \rA)
167 		BSRLI10(\rD, \rA)
169 		BSRLI2(\rD, \rA)
170 		BSRLI10(\rD, \rD)
172 		BSRLI4(\rD, \rA)
173 		BSRLI10(\rD, \rD)
175 		BSRLI20(\rD, \rA)
177 		BSRLI4(\rD, \rA)
178 		BSRLI20(\rD, \rD)
180 		BSRLI4(\rD, \rA)
181 		BSRLI4(\rD, \rD)
182 		BSRLI20(\rD, \rD)
270 /*  3 - Instruction bus error exception */
404 	lbui	r5, r3, 3;
454 	sbi	r4, r3, 3;
844 load4:	lbui	r5, r4, 3;
845 	sbi	r5, r6, 3;
878 	lbui	r3, r5, 3;
880 store4:	sbi	r3, r4, 3;	/* Delay slot */
892 	lbui	r3, r5, 3;
950 lw_r3:		R3_TO_LWREG_V	(3);
984 sw_r3:		SWREG_TO_R3_V	(3);
1018 lw_r3_vm:	R3_TO_LWREG_VM_V	(3);
1052 sw_r3_vm:	SWREG_TO_R3_VM_V	(3);