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/linux-6.12.1/arch/arm64/tools/
Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
44 # NI - Not implemented
45 # IMP - Implemented
52 Res0 63:32
57 Res0 63:31
64 Res0 63:36
68 Field 32 EMBWE
92 Res0 63:32
97 Res0 63:32
102 Res0 63:1
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/linux-6.12.1/drivers/infiniband/hw/irdma/
Ddefs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
141 #define IRDMA_QP_WQE_MIN_SIZE 32
198 IRDMA_OP_MC_DESTROY = 32,
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
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Duda_d.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2016 - 2021 Intel Corporation */
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
70 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32)
78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
83 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)
85 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)
86 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32)
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/linux-6.12.1/arch/x86/include/asm/
Dsev-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
23 /* GHCBData[63:48] */ \
25 /* GHCBData[47:32] */ \
26 (((_min) & 0xffff) << 32) | \
33 #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff)
38 #define GHCB_MSR_CPUID_FUNC_POS 32
40 #define GHCB_MSR_CPUID_VALUE_POS 32
53 /* GHCBData[63:32] */ \
54 (((unsigned long)fn) << 32))
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/linux-6.12.1/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_RF.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
24 pDM_Odm->CutVersion << 24 | in CheckPositive()
25 pDM_Odm->SupportPlatform << 16 | in CheckPositive()
26 pDM_Odm->PackageType << 12 | in CheckPositive()
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/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_npc_hash.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 (((hdr_ofs) << 32) | ((bytesm1) << 16) | \
104 GENMASK_ULL(63, 0),
105 GENMASK_ULL(63, 0),
108 GENMASK_ULL(63, 0),
109 GENMASK_ULL(63, 0),
115 GENMASK_ULL(63, 0),
116 GENMASK_ULL(63, 0),
119 GENMASK_ULL(63, 0),
120 GENMASK_ULL(63, 0),
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/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-pip-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
74 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
75 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
76 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
77 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
82 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
83 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
84 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
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Dcvmx-led-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
88 uint64_t reserved_1_63:63;
92 uint64_t reserved_1_63:63;
101 uint64_t reserved_1_63:63;
105 uint64_t reserved_1_63:63;
114 uint64_t reserved_1_63:63;
118 uint64_t reserved_1_63:63;
179 uint64_t reserved_32_63:32;
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/linux-6.12.1/Documentation/translations/zh_CN/core-api/
Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
75 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
87 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
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/linux-6.12.1/drivers/net/wireless/realtek/rtw88/
Drtw8703b_tables.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
19 /* Regd: FCC -> 0, ETSI -> 2, MKK -> 1
20 * Band: 2.4G -> 0, 5G -> 1
21 * Bandwidth (bw): 20M -> 0, 40M -> 1, 80M -> 2, 160M -> 3
22 * Rate Section (rs): CCK -> 0, OFDM -> 1, HT -> 2, VHT -> 3
27 {1, 0, 0, 0, 1, 32},
30 {1, 0, 0, 0, 2, 32},
33 {1, 0, 0, 0, 3, 32},
36 {1, 0, 0, 0, 4, 32},
39 {1, 0, 0, 0, 5, 32},
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Drtw8821c_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
6026 { 0, 0, 0, 0, 2, 32, },
6029 { 3, 0, 0, 0, 2, 32, },
6032 { 6, 0, 0, 0, 2, 32, },
6034 { 8, 0, 0, 0, 2, 32, },
6038 { 0, 0, 0, 0, 3, 32, },
6041 { 3, 0, 0, 0, 3, 32, },
6044 { 6, 0, 0, 0, 3, 32, },
6046 { 8, 0, 0, 0, 3, 32, },
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/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dtable.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
2899 "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
2900 "MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
2902 "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
2903 "MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
2905 "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
2906 "MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
2908 "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
2909 "MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
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/linux-6.12.1/drivers/net/ethernet/ibm/ehea/
Dehea_phyp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 while (((1U << ld) - 1) < queue_entries) in get_order_of_qentries()
25 return ld - 1; in get_order_of_qentries()
144 #define H_ALL_RES_QP_RES_TYP EHEA_BMASK_IBM(56, 63)
148 #define H_ALL_RES_QP_PD EHEA_BMASK_IBM(32, 63)
160 #define H_ALL_RES_QP_MAX_R3SGE EHEA_BMASK_IBM(61, 63)
165 #define H_ALL_RES_QP_PORT_NUM EHEA_BMASK_IBM(48, 63)
176 #define H_ALL_RES_QP_ACT_R2WQE EHEA_BMASK_IBM(32, 47)
177 #define H_ALL_RES_QP_ACT_R3WQE EHEA_BMASK_IBM(48, 63)
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/linux-6.12.1/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
44 perspective, bit 63 always means bit offset 7 of byte 7, albeit only
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/linux-6.12.1/drivers/net/ethernet/sfc/falcon/
Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * ef4_dword_t) to be little-endian.
34 #define EF4_DWORD_0_WIDTH 32
35 #define EF4_DWORD_1_LBN 32
36 #define EF4_DWORD_1_WIDTH 32
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/linux-6.12.1/drivers/net/ethernet/sfc/
Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * efx_dword_t) to be little-endian.
36 #define EFX_DWORD_0_WIDTH 32
37 #define EFX_DWORD_1_LBN 32
38 #define EFX_DWORD_1_WIDTH 32
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Def10_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2012-2017 Solarflare Communications Inc.
13 * E<type>_<min-rev><max-rev>_
18 * -------------------------------------------------------------
23 * <min-rev> is the first revision to which the definition applies:
28 * then <max-rev> is the last revision to which the definition applies;
42 #define ERF_DZ_HW_REV_ID_WIDTH 32
49 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32
54 #define ERF_DZ_ISR_REG_WIDTH 32
59 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32
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/linux-6.12.1/drivers/net/ethernet/sfc/siena/
Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * efx_dword_t) to be little-endian.
34 #define EFX_DWORD_0_WIDTH 32
35 #define EFX_DWORD_1_LBN 32
36 #define EFX_DWORD_1_WIDTH 32
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/linux-6.12.1/include/crypto/
Dgf128mul.h1 /* gf128mul.h - GF(2^128) multiplication functions
16 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
59 * http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf
61 * The elements of GF(2^128) := GF(2)[X]/(X^128-X^7-X^2-X^1-1) can
73 * in every byte in little-endian order and the bytes themselves also in
74 * little endian order. I will call this lle (little-little-endian).
81 * bytes also. This is bbe (big-big-endian). Now the buffer above
86 * Both of the above formats are easy to implement on big-endian
94 * The common machine word-size is smaller than 128 bits, so to make
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dpsp_gfx_if.h46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
108 /* PSP boot config sub-commands */
126 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
129 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
152 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
186 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
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/linux-6.12.1/arch/s390/include/asm/
Dnmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define MCIC_SUBCLASS_MASK (1ULL<<63 | 1ULL<<62 | 1ULL<<61 | \
22 #define MCCK_CODE_SYSTEM_DAMAGE BIT(63)
23 #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5)
24 #define MCCK_CODE_CP BIT(63 - 9)
25 #define MCCK_CODE_STG_ERROR BIT(63 - 16)
26 #define MCCK_CODE_STG_KEY_ERROR BIT(63 - 18)
27 #define MCCK_CODE_STG_DEGRAD BIT(63 - 19)
28 #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20)
29 #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23)
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/linux-6.12.1/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
34 * Many hardware clock counters are only 32 bits wide and therefore have
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dmsc01_ic.h20 #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
22 #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
24 #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
26 #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
40 #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
41 #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
42 #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
43 #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
131 * Soc-it interrupts are configurable.
/linux-6.12.1/drivers/clk/xilinx/
Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
11 #include <linux/clk-provider.h>
16 #include <linux/mfd/syscon/xlnx-vcu.h>
22 #include <dt-bindings/clock/xlnx-vcu.h>
50 * struct xvcu_device - Xilinx VCU init device structure
73 .reg_bits = 32,
74 .val_bits = 32,
81 * struct xvcu_pll_cfg - Helper data
99 { 25, 3, 10, 3, 63, 1000 },
[all …]
/linux-6.12.1/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.h1 /* SPDX-License-Identifier: GPL-2.0-only */
100 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
181 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
182 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
185 #define Q_ENT(q, p) ((q)->base + \
186 Q_IDX(&((q)->llq), p) * \
187 (q)->ent_dwords)
249 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
279 #define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
342 #define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
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