arm/arm-smmu-v3/arm-smmu-v3.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
100 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
181 #define Q_IDX(llq, p)			((p) & ((1 << (llq)->max_n_shift) - 1))
182 #define Q_WRP(llq, p)			((p) & (1 << (llq)->max_n_shift))
185 #define Q_ENT(q, p)			((q)->base +			\
186 					 Q_IDX(&((q)->llq), p) *	\
187 					 (q)->ent_dwords)
249 #define STRTAB_STE_0_S1CDMAX		GENMASK_ULL(63, 59)
279 #define STRTAB_STE_2_VTCR		GENMASK_ULL(50, 32)
342 #define CTXDESC_CD_0_TCR_IPS		GENMASK_ULL(34, 32)
353 #define CTXDESC_CD_0_ASID		GENMASK_ULL(63, 48)
366 #define CMDQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
386 #define CMDQ_PREFETCH_0_SID		GENMASK_ULL(63, 32)
388 #define CMDQ_PREFETCH_1_ADDR_MASK	GENMASK_ULL(63, 12)
391 #define CMDQ_CFGI_0_SID			GENMASK_ULL(63, 32)
398 #define CMDQ_TLBI_0_VMID		GENMASK_ULL(47, 32)
399 #define CMDQ_TLBI_0_ASID		GENMASK_ULL(63, 48)
403 #define CMDQ_TLBI_1_VA_MASK		GENMASK_ULL(63, 12)
407 #define CMDQ_ATC_0_SID			GENMASK_ULL(63, 32)
410 #define CMDQ_ATC_1_ADDR_MASK		GENMASK_ULL(63, 12)
413 #define CMDQ_PRI_0_SID			GENMASK_ULL(63, 32)
421 #define CMDQ_RESUME_0_SID		GENMASK_ULL(63, 32)
430 #define CMDQ_SYNC_0_MSIDATA		GENMASK_ULL(63, 32)
436 #define EVTQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
447 #define EVTQ_0_SID			GENMASK_ULL(63, 32)
456 #define EVTQ_2_ADDR			GENMASK_ULL(63, 0)
462 #define PRIQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
465 #define PRIQ_0_SSID			GENMASK_ULL(51, 32)
471 #define PRIQ_0_SSID_V			(1UL << 63)
474 #define PRIQ_1_ADDR_MASK		GENMASK_ULL(63, 12)
476 /* High-level queue structures */
494 	/* Command-specific fields */
613 	return cmdq->supports_cmd ? cmdq->supports_cmd(ent) : true;  in arm_smmu_cmdq_supports_cmd()
632 /* High-level stream table and context descriptor structures */
660 	return cfg->linear.table || cfg->l2.l1tab;  in arm_smmu_cdtab_allocated()
666 	return cd_table->used_ssids;  in arm_smmu_ssids_in_use()
924 	return -ENODEV;  in arm_smmu_master_enable_sva()
929 	return -ENODEV;  in arm_smmu_master_disable_sva()
949 	return ERR_PTR(-ENODEV);  in tegra241_cmdqv_probe()