hw/irdma/defs.h

1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 	((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
141 #define IRDMA_QP_WQE_MIN_SIZE	32
198 	IRDMA_OP_MC_DESTROY			= 32,
360 	(((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 	(((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
376 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
380 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
382 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
384 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
385 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
390 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
394 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
397 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
406 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
410 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
412 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
415 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
417 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
418 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
420 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
421 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
431 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
432 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
436 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
443 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
445 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
449 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
451 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
466 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
472 #define IRDMA_CQ_VALID BIT_ULL(63)
477 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
482 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
484 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
486 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
496 #define IRDMA_CEQE_VALID BIT_ULL(63)
502 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
509 #define IRDMA_AEQE_VALID BIT_ULL(63)
512 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
516 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
529 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
530 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
540 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
548 #define IRDMA_CQPSQ_QP_OP_S 32
573 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
589 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
614 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
624 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
626 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
628 /* Manage Push Page - MPP */
638 /* Upload Context - UCTX */
650 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
665 #define IRDMA_COMMIT_FPM_BASE_S 32
671 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
672 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
682 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
684 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
690 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
725 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
727 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
728 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
738 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
739 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
740 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
742 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
746 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
747 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
754 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
756 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
758 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
760 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
765 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
767 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
769 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
770 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
773 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
775 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
777 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
779 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
781 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
782 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
784 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
785 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
786 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
791 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
793 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
795 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
811 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
812 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
819 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
826 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
828 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
830 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
834 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
835 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
837 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
848 #define IRDMAQPSQ_VALID BIT_ULL(63)
851 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
852 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
855 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
858 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
867 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
877 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
890 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
892 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
909 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
911 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
912 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
914 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
915 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
916 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
917 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
922 		(_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
927 		(_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
932 		(_ceq)->ceqe_base[_pos].buf  \
944 		(_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf  \
949 		((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
970 			(_retcode) = -ENOMEM; \
981 			(_retcode) = -ENOMEM; \
992 			(_retcode) = -ENOMEM; \
999 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1003 			(_retcode) = -ENOMEM; \
1023 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1))  \
1028 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2))  \
1033 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3))  \
1038 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257))  \
1043 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258))  \
1047 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259))  \
1056 		(((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1061 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1066 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1076 	IRDMA_WQE_SIZE_32  = 32,
1089 enum {	IRDMA_Q_ALIGNMENT_M		 = (128 - 1),
1090 	IRDMA_AEQ_ALIGNMENT_M		 = (256 - 1),
1091 	IRDMA_Q2_ALIGNMENT_M		 = (256 - 1),
1092 	IRDMA_CEQ_ALIGNMENT_M		 = (256 - 1),
1093 	IRDMA_CQ0_ALIGNMENT_M		 = (256 - 1),
1094 	IRDMA_HOST_CTX_ALIGNMENT_M	 = (4 - 1),
1095 	IRDMA_SHADOWAREA_M		 = (128 - 1),
1096 	IRDMA_FPM_QUERY_BUF_ALIGNMENT_M	 = (4 - 1),
1097 	IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1116  * set_64bit_val - set 64 bit value to hw wqe
1127  * set_32bit_val - set 32 bit value to hw wqe
1138  * get_64bit_val - read 64 bit value from wqe
1149  * get_32bit_val - read 32 bit value from wqe
1152  * @val: return 32 bit value