Home
last modified time | relevance | path

Searched +full:3 +full:- +full:c22 (Results 1 – 25 of 321) sorted by relevance

12345678910>>...13

/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dtqmls104xa-mbls10xxa-fman.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2019,2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
21 phy-handle = <&rgmii_phy1>;
22 phy-connection-type = "rgmii";
23 phy-mode = "rgmii-id";
28 phy-handle = <&rgmii_phy2>;
29 phy-connection-type = "rgmii";
30 phy-mode = "rgmii-id";
[all …]
Dtqmls1088a-mbls10xxa-mc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
15 i2c-bus = <&sfp1_i2c>;
16 mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
17 los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
18 tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
19 tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
24 i2c-bus = <&sfp2_i2c>;
[all …]
/linux-6.12.1/rust/kernel/net/phy/
Dreg.rs1 // SPDX-License-Identifier: GPL-2.0
24 /// C22 and C45 PHY registers.
30 /// // read C22 BMCR register
31 /// dev.read(C22::BMCR);
35 /// // Checks the link status as reported by registers in the C22 namespace
37 /// dev.genphy_read_status::<phy::C22>();
45 fn read(&self, dev: &mut Device) -> Result<u16>; in read()
48 fn write(&self, dev: &mut Device, val: u16) -> Result; in write()
51 fn read_status(dev: &mut Device) -> Result<u16>; in read_status()
56 pub struct C22(u8); struct
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
24 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
Dkirkwood-guruplug-server-plus.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
9 …compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281…
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pmx_led_health_r: pmx-led-health-r {
27 pmx_led_health_g: pmx-led-health-g {
31 pmx_led_wmode_r: pmx-led-wmode-r {
35 pmx_led_wmode_g: pmx-led-wmode-g {
[all …]
/linux-6.12.1/arch/mips/boot/dts/cavium-octeon/
Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
34 tx-delay = <0x10>;
[all …]
/linux-6.12.1/drivers/net/phy/
Dmicrochip_t1s.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Microchip 10BASE-T1S PHYs
37 * W 0x1F 0x008B 0x0404 ------
41 * W 0x1F 0x0099 0x7F80 ------
186 cfg_results[3] = (cfg_params[3] & 0xC0C0) | in lan865x_setup_cfgparam()
201 …Documents/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.… in lan865x_revb0_config_init()
220 /* The chip completes a reset in 3us, we might get here earlier than in lan867x_revb1_config_init()
234 return -ENODEV; in lan867x_revb1_config_init()
239 …aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf in lan867x_revb1_config_init()
259 * - always reports link up in lan86xx_read_status()
[all …]
/linux-6.12.1/arch/arm/boot/dts/aspeed/
Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dhisilicon-hip04-net.txt6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
26 - compatible: should be "hisilicon,mdio".
27 - Inherits from MDIO bus node binding [2]
34 #address-cells = <1>;
35 #size-cells = <0>;
[all …]
Dbrcm,bcmgenet.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Doug Berger <opendmb@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - brcm,genet-v1
17 - brcm,genet-v2
18 - brcm,genet-v3
19 - brcm,genet-v4
20 - brcm,genet-v5
[all …]
/linux-6.12.1/arch/arm/boot/dts/moxa/
Dmoxart-uc7112lx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
7 /dts-v1/;
11 model = "MOXA UC-7112-LX";
12 compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
28 compatible = "numonyx,js28f128", "cfi-flash";
30 bank-width = <2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3568-fastrhino-r68s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
[all …]
Drk3566-orangepi-3b-v1.1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-orangepi-3b.dtsi"
8 model = "Xunlong Orange Pi 3B v1.1";
9 compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566";
13 vccio5-supply = <&vcc_3v3>;
17 phy-handle = <&rgmii_phy1>;
22 rgmii_phy1: ethernet-phy@1 {
23 compatible = "ethernet-phy-ieee802.3-c22";
25 reset-assert-us = <20000>;
[all …]
Drk3566-radxa-zero-3e.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-radxa-zero-3.dtsi"
8 model = "Radxa ZERO 3E";
9 compatible = "radxa,zero-3e", "rockchip,rk3566";
18 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
19 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
21 phy-handle = <&rgmii_phy1>;
22 phy-mode = "rgmii-id";
23 phy-supply = <&vcc_3v3>;
[all …]
Drk3328-nanopi-r2c.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-nanopi-r2s.dts"
14 compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
18 phy-handle = <&yt8521s>;
23 /delete-node/ ethernet-phy@1;
25 yt8521s: ethernet-phy@3 {
26 compatible = "ethernet-phy-ieee802.3-c22";
27 reg = <3>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/ls/
Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2l-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2l.dtsi"
13 compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
Dkeystone-k2e-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
Dkeystone-k2hk-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2hk.dtsi"
13 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
31 unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */ in sxgbe_mdio_busy_wait()
39 return -EBUSY; in sxgbe_mdio_busy_wait()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
49 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
60 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
70 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); in sxgbe_mdio_c22()
74 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
82 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access_c22()
85 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c22()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-one-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "sun50i-h6-orangepi.dtsi"
9 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
15 reg_gmac_3v3: gmac-3v3 {
16 compatible = "regulator-fixed";
17 regulator-name = "vcc-gmac-3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 startup-delay-us = <100000>;
21 enable-active-high;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6ul-tx6ul-mainboard.dts2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
44 #include "imx6ul-tx6ul.dtsi"
47 model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
48 compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
51 lcdif-24bit-pins-a = &pinctrl_disp0_3;
53 /delete-property/ mmc1;
57 /delete-node/ sound;
61 xceiver-supply = <&reg_3v3>;
[all …]
Dimx6sx-udoo-neo-basic.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx6sx-udoo-neo.dtsi"
21 phy-handle = <&ethphy1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 ethphy1: ethernet-phy@0 {
29 compatible = "ethernet-phy-ieee802.3-c22";
/linux-6.12.1/drivers/gpu/drm/sun4i/
Dsun8i_csc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
60 * z' = c20 * (x + d0) + c21 * (y + d1) + c22 * (z + d2) + const2
70 * c20 c21 c22 [d2 const2]
73 static const u32 yuv2rgb_de3[2][3][12] = {
128 if ((i & 3) == 1) in sun8i_csc_set_coefficients()
130 else if ((i & 3) == 2) in sun8i_csc_set_coefficients()
131 base_reg = SUN8I_CSC_COEFF(base, i - 1); in sun8i_csc_set_coefficients()
161 if ((i & 3) == 1) in sun8i_de3_ccsc_set_coefficients()
165 else if ((i & 3) == 2) in sun8i_de3_ccsc_set_coefficients()
168 i - 1); in sun8i_de3_ccsc_set_coefficients()
[all …]
/linux-6.12.1/drivers/net/mdio/
Dmdio-cavium.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009-2016 Cavium, Inc.
11 #include "mdio-cavium.h"
18 if (m == p->mode) in cavium_mdiobus_set_mode()
21 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
24 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
25 p->mode = m; in cavium_mdiobus_set_mode()
39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
45 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_c45_addr()
52 smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
[all …]

12345678910>>...13