net/phy/microchip_t1s.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Driver for Microchip 10BASE-T1S PHYs
37  * W   0x1F 0x008B 0x0404 ------
41  * W   0x1F 0x0099 0x7F80 ------
186 	cfg_results[3] = (cfg_params[3] & 0xC0C0) |  in lan865x_setup_cfgparam()
201 …Documents/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.…  in lan865x_revb0_config_init()
220 	/* The chip completes a reset in 3us, we might get here earlier than  in lan867x_revb1_config_init()
234 			return -ENODEV;  in lan867x_revb1_config_init()
239 …aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf  in lan867x_revb1_config_init()
259 	 *  - always reports link up  in lan86xx_read_status()
260 	 *  - only supports 10MBit half duplex  in lan86xx_read_status()
261 	 *  - does not support auto negotiate  in lan86xx_read_status()
263 	phydev->link = 1;  in lan86xx_read_status()
264 	phydev->duplex = DUPLEX_HALF;  in lan86xx_read_status()
265 	phydev->speed = SPEED_10;  in lan86xx_read_status()
266 	phydev->autoneg = AUTONEG_DISABLE;  in lan86xx_read_status()
271 /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and
272  * C45 registers space. If the PHY is discovered via C22 bus protocol it assumes
273  * it uses C22 protocol and always uses C22 registers indirect access to access
275  * C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C45
284 	struct mii_bus *bus = phydev->mdio.bus;  in lan865x_phy_read_mmd()
285 	int addr = phydev->mdio.addr;  in lan865x_phy_read_mmd()
293 	struct mii_bus *bus = phydev->mdio.bus;  in lan865x_phy_write_mmd()
294 	int addr = phydev->mdio.addr;  in lan865x_phy_write_mmd()
334 MODULE_DESCRIPTION("Microchip 10BASE-T1S PHYs driver");