Lines Matching +full:3 +full:- +full:c22
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <100000000>;
37 clock-output-names = "refclk-sys";
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <100000000>;
44 clock-output-names = "refclk-pass";
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <100000000>;
51 clock-output-names = "refclk-ddr3a";
89 #address-cells = <2>;
90 #size-cells = <1>;
91 clock-ranges;
94 ti,cs-chipselect = <0>;
96 ti,cs-min-turnaround-ns = <12>;
97 ti,cs-read-hold-ns = <6>;
98 ti,cs-read-strobe-ns = <23>;
99 ti,cs-read-setup-ns = <9>;
100 ti,cs-write-hold-ns = <8>;
101 ti,cs-write-strobe-ns = <23>;
102 ti,cs-write-setup-ns = <8>;
105 compatible = "ti,keystone-nand","ti,davinci-nand";
106 #address-cells = <1>;
107 #size-cells = <1>;
111 ti,davinci-chipselect = <0>;
112 ti,davinci-mask-ale = <0x2000>;
113 ti,davinci-mask-cle = <0x4000>;
114 ti,davinci-mask-chipsel = <0>;
115 nand-ecc-mode = "hw";
116 ti,davinci-ecc-bits = <4>;
117 nand-on-flash-bbt;
120 label = "u-boot";
122 read-only;
128 read-only;
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "micron,n25q128a11", "jedec,spi-nor";
144 spi-max-frequency = <54000000>;
145 m25p,fast-read;
149 label = "u-boot-spl";
151 read-only;
163 ethphy0: ethernet-phy@0 {
164 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
168 ethphy1: ethernet-phy@1 {
169 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
175 memory-region = <&dsp_common_memory>;