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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
27 - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
39 - apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
[all …]
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
36 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
37 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
46 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
47 * 5 Gbps (QSGMII/USGMII)
48 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
49 * 10 Gbps (10G-USGMII)
50 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
[all …]
Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
/linux-6.12.1/drivers/scsi/mvsas/
Dmv_94xx.h122 VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
[all …]
/linux-6.12.1/Documentation/scsi/
Dbfa.rst16 1657:0013:1657:0014 425 4Gbps dual port FC HBA
17 1657:0013:1657:0014 825 8Gbps PCIe dual port FC HBA
18 1657:0013:103c:1742 HP 82B 8Gbps PCIedual port FC HBA
19 1657:0013:103c:1744 HP 42B 4Gbps dual port FC HBA
20 1657:0017:1657:0014 415 4Gbps single port FC HBA
21 1657:0017:1657:0014 815 8Gbps single port FC HBA
22 1657:0017:103c:1741 HP 41B 4Gbps single port FC HBA
23 1657:0017:103c 1743 HP 81B 8Gbps single port FC HBA
24 1657:0021:103c:1779 804 8Gbps FC HBA for HP Bladesystem c-class
26 1657:0014:1657:0014 1010 10Gbps single port CNA - FCOE
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96712.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 title: Quad GMSL2 to CSI-2 Deserializer with GMSL1 Compatibility
15 CSI-2 D-PHY or C-PHY formatted outputs. The device allows each link to
21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
48 port@2:
50 description: GMSL Input 2
59 description: CSI-2 Output
112 data-lanes = <1 2 3 4>;
Dmaxim,max96717.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 title: MAX96717 CSI-2 to GMSL2 Serializer
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
39 const: 2
59 description: CSI-2 Input port
113 #gpio-cells = <2>;
123 data-lanes = <1 2 3 4>;
149 data-lanes = <1 2 3 4>;
Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
62 description: CSI-2 Output port
132 data-lanes = <1 2 3 4>;
147 #gpio-cells = <2>;
157 data-lanes = <1 2>;
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h35 LANE_COUNT_TWO = 2,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_arcturus.h37 #define NUM_MP0CLK_DPM_LEVELS 2
41 #define NUM_XGMI_LEVELS 2
58 #define FEATURE_DPM_UCLK_BIT 2
189 #define THROTTLER_TEMP_HOTSPOT_BIT 2
214 #define WORKLOAD_PPLIB_VIDEO_BIT 2
265 uint8_t Padding[2];
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
[all …]
Dsmu11_driver_if_sienna_cichlid.h35 #define NUM_SMNCLK_DPM_LEVELS 2
37 #define NUM_MP0CLK_DPM_LEVELS 2
46 #define NUM_MP1CLK_DPM_LEVELS 2
47 #define NUM_LINK_LEVELS 2
49 #define NUM_XGMI_LEVELS 2
72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board
78 #define FEATURE_DPM_GFX_GPO_BIT 2
197 #define THROTTLER_TEMP_HOTSPOT_BIT 2
221 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2
264 #define LED_DISPLAY_ERROR_BIT 2
[all …]
/linux-6.12.1/drivers/scsi/bfa/
Dbfad_attr.c193 fc_host_active_fc4s(shost)[2] = 1; in bfad_im_get_host_active_fc4s()
414 fc_host_supported_fc4s(vshost)[2] = 1; in bfad_im_vport_create()
747 "QLogic BR-series 4Gbps PCIe dual port FC HBA"); in bfad_im_model_desc_show()
750 "QLogic BR-series 8Gbps PCIe dual port FC HBA"); in bfad_im_model_desc_show()
753 "QLogic BR-series 4Gbps PCIe dual port FC HBA for HP"); in bfad_im_model_desc_show()
756 "QLogic BR-series 8Gbps PCIe dual port FC HBA for HP"); in bfad_im_model_desc_show()
759 "QLogic BR-series 10Gbps single port CNA"); in bfad_im_model_desc_show()
762 "QLogic BR-series 10Gbps dual port CNA"); in bfad_im_model_desc_show()
765 "QLogic BR-series 10Gbps CNA for IBM Blade Center"); in bfad_im_model_desc_show()
768 "QLogic BR-series 4Gbps PCIe single port FC HBA"); in bfad_im_model_desc_show()
[all …]
/linux-6.12.1/drivers/net/ethernet/ezchip/
Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
65 #define CFG_0_TX_FC_EN_SHIFT 2
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
125 #define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2
/linux-6.12.1/drivers/scsi/be2iscsi/
DKconfig3 tristate "Emulex 10Gbps iSCSI - BladeEngine 2"
11 10Gbps Storage adapter - BladeEngine 2.
/linux-6.12.1/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.c87 * - PHY, Clock and Mode setup for 2k && 4k modes
121 MESON_VENC_SOURCE_ENCP = 2,
185 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_read()
208 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_write()
300 if (mode_is_420) pixel_clock /= 2; in meson_hdmi_phy_setup_mode()
305 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
309 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
313 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
324 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
328 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
[all …]
/linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/
Dqos_lib.sh29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
Dsch_red_core.sh3 # This test sends a >1Gbps stream of traffic from H1, to the switch, which
4 # forwards it to a 1Gbps port. This 1Gbps stream is then looped back to the
5 # switch and forwarded to the port under test $swp3, which is also 1Gbps.
35 # | >1Gbps |
60 # | | | 1Gbps
83 echo 192.0.2.$((16 * (vlan - 10) + host))
123 host_create $h2 2
138 # 1Gbps.
289 ping_test $h2.10 $(ipaddr 3 10) " from host 2, vlan 10"
290 ping_test $h2.11 $(ipaddr 3 11) " from host 2, vlan 11"
[all …]
Dqos_mc_aware.sh39 # | >1Gbps | | >1Gbps |
48 # | | 1Gbps bottleneck |
261 scale=2
267 # degradation on 1Gbps link.
Dqos_ets_strict.sh6 # other with PCP of 2. Both streams converge at one egress port, where they are
7 # assigned TC of, respectively, 1 and 2, with strict priority configured between
17 # | e-qos-map 0:1 | | | | e-qos-map 0:2 |
24 # | >1Gbps | | >1Gbps |
33 # | | 1Gbps bottleneck |
81 ip link set dev $h2.222 type vlan egress-qos-map 0:2
119 lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:1,2:2,3:3,4:4,5:5,6:6,7:7
123 )"2:strict,"$(
167 devlink_tc_bind_pool_th_save $swp2 2 ingress
168 devlink_tc_bind_pool_th_set $swp2 2 ingress 0 6
[all …]
/linux-6.12.1/drivers/net/phy/
Drealtek.c48 #define RTL8211F_ALDPS_ENABLE BIT(2)
69 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
418 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", in rtl8211f_config_init()
422 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", in rtl8211f_config_init()
433 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", in rtl8211f_config_init()
437 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", in rtl8211f_config_init()
1339 .name = "RTL8226 2.5Gbps PHY",
1352 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1366 .name = "RTL8226-CG 2.5Gbps PHY",
1376 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-8040-puzzle-m801.dts81 mod-def0-gpios = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>;
94 /* SFP+ port 2: Activity */
107 led-2 {
108 /* SFP+ port 2: 10 Gbps indicator */
110 function-enumerator = <2>;
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
245 #cooling-cells = <2>;
251 #cooling-cells = <2>;
[all …]
/linux-6.12.1/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.h28 #define HCLGE_RD_FIRST_STATS_NUM 2
89 #define HCLGE_RSS_TC_SIZE_1 2
138 #define HCLGE_PF_ID_M GENMASK(2, 0)
152 #define HCLGE_IMP_RESET_BIT 2
183 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
189 #define HCLGE_SUPPORT_25G_BIT BIT(2)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
/linux-6.12.1/fs/smb/client/
Dcifs_debug.c180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
196 return "50Gbps"; in smb_speed_to_str()
198 return "56Gbps"; in smb_speed_to_str()
[all …]
/linux-6.12.1/include/rdma/
Dopa_port_info.h16 #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
29 #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
90 #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
111 /* reserved (1 << 2) */
118 OPA_PORT_PHYS_CONF_FIXED = 2,
146 /* Filter Raw In/Out bits 1 and 2 were removed */
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cx0_phy.c25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
63 return intel_tc_port_max_lane_count(dig_port) > 2 in intel_cx0_get_owned_lane_mask()
423 return 2; in intel_c10_get_tx_term_ctl()
467 int lane = ln / 2; in intel_cx0_phy_set_signal_levels()
468 int tx = ln % 2; in intel_cx0_phy_set_signal_levels()
482 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), in intel_cx0_phy_set_signal_levels()
513 .pll[2] = 0x30,
539 .pll[2] = 0xA2,
565 .pll[2] = 0xDA,
591 .pll[2] = 0xF8,
[all …]

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