Lines Matching +full:2 +full:gbps

122 	VSR_PHY_MODE10		= 0x0A * 4, /* Event Counter 2 */
143 	MVS_IRQ_COM_IN_I2O_IOP2        = (1 << 2),
180 		 * bit 2: 6Gbps support
181 		 * bit 1: 3Gbps support
182 		 * bit 0: 1.5Gbps support
188 		 * bit 5: G1 (1.5Gbps) Without SSC
189 		 * bit 4: G1 (1.5Gbps) with SSC
190 		 * bit 3: G2 (3.0Gbps) Without SSC
191 		 * bit 2: G2 (3.0Gbps) with SSC
192 		 * bit 1: G3 (6.0Gbps) without SSC
193 		 * bit 0: G3 (6.0Gbps) with SSC
196 		/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
212 	u8			_r_a:2;
218 	u32			_r_a:2;
236 	MVS_SGPIO_CFG0_BLINKA	= (1 << 2),
266 	MVS_SGPIO_CTRL_SDOUT_AUTO	= 2,
267 	MVS_SGPIO_CTRL_SDOUT_SHIFT	= 2,
280 	LED_BLINKA	= 2,
291 				MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 2) | \
312 #define SPI_CTRL_READ_94XX         	(1U << 2)