Lines Matching +full:2 +full:gbps
25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
63 return intel_tc_port_max_lane_count(dig_port) > 2 in intel_cx0_get_owned_lane_mask()
423 return 2; in intel_c10_get_tx_term_ctl()
467 int lane = ln / 2; in intel_cx0_phy_set_signal_levels()
468 int tx = ln % 2; in intel_cx0_phy_set_signal_levels()
482 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), in intel_cx0_phy_set_signal_levels()
513 .pll[2] = 0x30,
539 .pll[2] = 0xA2,
565 .pll[2] = 0xDA,
591 .pll[2] = 0xF8,
617 .pll[2] = 0x30,
643 .pll[2] = 0xA2,
669 .pll[2] = 0xF8,
695 .pll[2] = 0x3E,
721 .pll[2] = 0x84,
865 .clock = 1000000, /* 10 Gbps */
889 .clock = 1350000, /* 13.5 Gbps */
914 .clock = 2000000, /* 20 Gbps */
1091 .clock = 1350000, /* 13.5 Gbps */
1135 .pll[2] = 0xB2,
1161 .pll[2] = 0xC0,
1187 .pll[2] = 0x7A,
1213 .pll[2] = 0x7A,
1239 .pll[2] = 0x7A,
1264 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1274 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1284 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1294 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1304 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1314 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1324 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1334 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1344 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1354 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1364 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1374 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1384 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1394 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1404 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1414 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1424 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1434 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1444 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1454 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1464 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1474 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1484 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1494 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1504 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1514 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1524 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1534 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1544 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1554 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1564 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1574 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1584 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1594 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1604 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1614 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1624 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1634 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1644 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1654 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
2130 hw_state->pll[2]) / 2 + 16; in intel_c10pll_dump_hw_state()
2142 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
2166 mpll_multiplier = 2 * (multiplier >> 32); in intel_c20_compute_hdmi_tmds_pll()
2186 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2189 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2196 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | in intel_c20_compute_hdmi_tmds_pll()
2325 tx_rate_mult = 2; in intel_c20pll_calc_port_clock()
2342 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); in intel_c20pll_calc_port_clock()
2421 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2422 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2423 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2424 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2447 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2449 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2451 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2452 return 2; in intel_c20_get_dp_rate()
2453 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2455 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2457 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2459 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2461 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2463 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2465 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2467 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2469 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2471 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2485 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2486 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2487 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2489 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2490 return 2; in intel_c20_get_hdmi_rate()
2491 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2511 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2512 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2513 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2514 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2515 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2534 return 2; in intel_get_c20_custom_width()
2559 * 2. If there is a protocol switch from HDMI to DP or vice versa, clear in intel_c20_pll_program()
2664 pll_state->pll[2]) / 2 + 16; in intel_c10pll_calc_port_clock()
2672 tmpclk *= (hdmi_div ? 2 : 1); in intel_c10pll_calc_port_clock()
2889 int tx = i % 2 + 1; in intel_cx0_program_phy_lane()
2890 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_program_phy_lane()
2895 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_TX_CONTROL(tx, 2), in intel_cx0_program_phy_lane()
2947 /* 2. Bring PHY out of reset. */ in intel_cx0pll_enable()
3072 /* 2. Read back PORT_CLOCK_CTL REGISTER */ in intel_mtl_tbt_pll_enable()
3142 * 2. Follow the Display Voltage Frequency Switching Sequence Before in intel_cx0pll_disable()
3192 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. in intel_mtl_tbt_pll_disable()