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/linux-6.12.1/Documentation/virt/hyperv/ !
Doverview.rst1 .. SPDX-License-Identifier: GPL-2.0
6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
7 consists primarily of a bare-metal hypervisor plus a virtual machine
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
20 --------------------------------------
21 Linux guests communicate with Hyper-V in four different ways:
23 * Implicit traps: As defined by the x86/x64 or arm64 architecture,
[all …]
Dclocks.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
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/linux-6.12.1/drivers/staging/media/meson/vdec/ !
Dcodec_h264.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <media/v4l2-mem2mem.h>
8 #include <media/videobuf2-dma-contig.h>
26 #define CMD_SRC_CHANGE 1
32 #define SEI_DATA_READY BIT(15)
45 #define ERROR_FLAG BIT(9)
57 #define AR_PRESENT_FLAG BIT(0)
62 * This is a 16x16 encoded picture that will trigger drain firmware-side.
72 0x63, 0x6f, 0x64, 0x65, 0x63, 0x20, 0x2d, 0x20, 0x43, 0x6f, 0x70, 0x79,
75 0x77, 0x77, 0x77, 0x2e, 0x76, 0x69, 0x64, 0x65, 0x6f, 0x6c, 0x61, 0x6e,
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/linux-6.12.1/include/linux/ !
Dcper.h1 /* SPDX-License-Identifier: GPL-2.0-only */
80 /* Non-Maskable Interrupt */
87 0xD4, 0x64, 0xB3, 0x8F)
96 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
103 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
110 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
153 /* If set, the component must be re-initialized or re-enabled prior to use */
204 /* PCI/PCI-X Bus */
214 0xDE, 0x3E, 0x2C, 0x64)
280 #define CPER_ARM_VALID_MPIDR BIT(0)
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/linux-6.12.1/drivers/media/platform/qcom/venus/ !
Dhfi_venus_io.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
30 #define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1
42 #define CPU_CS_SCIACMDARG0_PC_READY BIT(8)
43 #define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30)
56 #define UC_REGION_ADDR 0x64
117 #define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET 0x64
121 #define WRAPPER_CPU_AXI_HALT_HALT BIT(16)
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/linux-6.12.1/include/video/ !
Dtdfx.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/i2c-algo-bit.h>
34 #define HWCURLOC 0x64
76 #define COLORFORE (0x00100000 + 0x64)
91 #define AUTOINC_DSTX BIT(10)
92 #define AUTOINC_DSTY BIT(11)
98 #define STATUS_RETRACE BIT(6)
99 #define STATUS_BUSY BIT(9)
100 #define MISCINIT1_CLUT_INV BIT(0)
101 #define MISCINIT1_2DBLOCK_DIS BIT(15)
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/linux-6.12.1/drivers/bus/mhi/ !
Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 #define ECABAP_HIGHER 0x64
62 #define BHI_OEMPKHASH(n) (0x64 + (0x4 * (n)))
81 #define BHIE_RXVECADDR_HIGH_OFFS 0x64
112 #define MHICTRL_RESET_MASK BIT(1)
114 #define MHISTATUS_SYSERR_MASK BIT(2)
115 #define MHISTATUS_READY_MASK BIT(0)
144 #define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
145 #define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
146 #define MHI_TRE_GET_CMD_TYPE(tre) FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))
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/linux-6.12.1/drivers/staging/media/atomisp/i2c/ !
Dmt9m114.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-ctrls.h>
31 #include <linux/v4l2-mediabus.h>
32 #include <media/media-entity.h>
42 #define MISENSOR_8BIT 1
57 #define MISENSOR_AWB_STEADY BIT(0) /* awb steady */
58 #define MISENSOR_AE_READY BIT(3) /* ae status ready */
65 #define MISENSOR_FLIP_EN 1
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/linux-6.12.1/include/sound/ !
Dtas2781.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 // Copyright (C) 2022 - 2024 Texas Instruments Incorporated
12 // Author: Shenghao Ding <shenghao-ding@ti.com>
13 // Author: Kevin Lu <kevin-lu@ti.com>
19 #include "tas2781-dsp.h"
22 #define TAS2781_DRV_VER 1
47 #define TASDEVICE_REG_SWRESET_RESET BIT(0)
53 #define TASDEVICE_XM_A1_REG TASDEVICE_REG(0x64, 0x63, 0x3c)
55 #define TASDEVICE_XM_A2_REG TASDEVICE_REG(0x64, 0x63, 0x38)
61 #define TAS2781_AMP_LEVEL_MASK GENMASK(5, 1)
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/linux-6.12.1/Documentation/trace/ !
Duprobetracer.rst2 Uprobe-tracer: Uprobe-based Event Tracing
9 --------
13 Similar to the kprobe-event tracer, this doesn't need to be activated via
18 However unlike kprobe-event tracer, the uprobe event interface expects the
26 -------------------------
32 -:[GRP/][EVENT] : Clear uprobe or uretprobe event
47 $retval : Fetch return value.(\*1)
49 +|-[u]OFFS(FETCHARG) : Fetch memory at FETCHARG +|- OFFS address.(\*2)(\*3)
54 (x8/x16/x32/x64), "string" and bitfield are supported.
56 (\*1) only for return probe.
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/linux-6.12.1/drivers/gpu/drm/rockchip/ !
Drockchip_drm_vop2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author:Mark Yao <mark.yao@rock-chips.com>
14 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
16 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
17 #define VOP2_FEATURE_HAS_VO0_GRF BIT(1)
18 #define VOP2_FEATURE_HAS_VO1_GRF BIT(2)
19 #define VOP2_FEATURE_HAS_VOP_GRF BIT(3)
20 #define VOP2_FEATURE_HAS_SYS_PMU BIT(4)
22 #define WIN_FEATURE_AFBDC BIT(0)
23 #define WIN_FEATURE_CLUSTER BIT(1)
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/linux-6.12.1/include/linux/mfd/ !
Dtps65912.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
117 #define TPS65912_VERNUM 0x64
118 #define TPS6591X_MAX_REGISTER 0x64
121 #define TPS65912_INT_STS_PWRHOLD_F BIT(0)
122 #define TPS65912_INT_STS_VMON BIT(1)
123 #define TPS65912_INT_STS_PWRON BIT(2)
124 #define TPS65912_INT_STS_PWRON_LP BIT(3)
125 #define TPS65912_INT_STS_PWRHOLD_R BIT(4)
126 #define TPS65912_INT_STS_HOTDIE BIT(5)
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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ !
Danalogix,anx7625.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
22 maxItems: 1
26 maxItems: 1
28 enable-gpios:
30 maxItems: 1
32 reset-gpios:
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/linux-6.12.1/drivers/irqchip/ !
Dirq-imx-mu-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Based on drivers/mailbox/imx-mailbox.c
27 #include "irq-msi-lib.h"
48 IMX_MU_V2 = BIT(1),
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
80 return ioread32(msi_data->regs + offs); in imx_mu_read()
88 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
89 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
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/linux-6.12.1/drivers/acpi/pmic/ !
Dintel_pmic_bytcrc.c1 // SPDX-License-Identifier: GPL-2.0
15 #define PWR_SOURCE_SELECT BIT(1)
23 .bit = ??,
28 .bit = 0x00,
29 }, /* SYSX -> VSYS_SX */
33 .bit = 0x00,
34 }, /* SYSU -> VSYS_U */
37 .reg = 0x64,
38 .bit = 0x00,
39 }, /* SYSS -> VSYS_S */
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/linux-6.12.1/lib/math/ !
Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
28 /* Not needed on 64bit architectures */
36 uint64_t res, d = 1; in __div64_32()
39 /* Reduce the thing a bit first */ in __div64_32()
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/linux-6.12.1/drivers/iio/chemical/ !
Dbme680.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define BME680_SPI_MEM_PAGE_BIT BIT(4)
11 #define BME680_SPI_MEM_PAGE_1_VAL 1
18 #define BME680_GAS_STAB_BIT BIT(4)
27 #define BME680_MODE_MASK GENMASK(1, 0)
28 #define BME680_MODE_FORCED 1
33 #define BME680_FILTER_COEFF_VAL BIT(1)
46 #define BME680_REG_GAS_WAIT_0 0x64
51 #define BME680_RUN_GAS_MASK BIT(4)
55 #define BME680_NEW_DATA_BIT BIT(7)
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/linux-6.12.1/Documentation/devicetree/bindings/phy/ !
Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
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/linux-6.12.1/crypto/asymmetric_keys/ !
Dselftest_rsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Self-tests for PKCS#7 RSA signature verification.
15 /* 4096-bit RSA certificate */
45 "\xe8\xde\x09\x31\x89\xed\x0e\x11\xa1\xfa\x8a\xe9\xe9\x64\x59\x62"
73 "\xcc\x4d\x14\x61\x64\x81\x93\xd3\x33\xed\xc8\xff\xf1\x78\xcc\x5f"
100 "\x0a\xd1\x95\x76\x8d\xec\x9e\xdd\x0b\x15\x97\x64\xad\xe5\xf2\x62"
109 "\x74\x20\x64\x61\x74\x61\x20\x75\x73\x65\x64\x20\x66\x6f\x72\x20"
116 /* RSA signature using PKCS#1 v1.5 padding with SHA-256 */
141 "\x22\x66\xc5\x3b\xc1\xba\xfc\x53\x18\x98\xe2\x21\x64\xc6\x52\x87"
157 "\xdd\x23\xd6\x53\xb1\x74\x77\x12\xf7\x9c\xf0\x9a\x6b\xf7\xa9\x64"
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/linux-6.12.1/sound/soc/ti/ !
Domap-dmic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * omap-dmic.h -- OMAP Digital Microphone Controller
27 #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64
29 /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
30 #define OMAP_DMIC_IRQ (1 << 0)
31 #define OMAP_DMIC_IRQ_FULL (1 << 1)
32 #define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2)
33 #define OMAP_DMIC_IRQ_EMPTY (1 << 3)
36 /* DMIC_DMAENABLE bit fields */
39 /* DMIC_CTRL bit fields */
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/linux-6.12.1/sound/pci/ !
Dazt3328.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
6 * "WRITE_ONLY" == register does not indicate actual bit values */
25 /* able to reactivate output after output muting due to 8/16bit
27 * 0x0001 is the only bit that's able to start the DMA counter */
31 /* able to reactivate output after output muting due to 8/16bit
42 * (bit 1 of port 0x64 indicates interrupt for one of these three types)
47 #define IRQ_FINISHED_DMABUF_1 0x0002 /* 1st dmabuf finished & ACK */
52 /* start address of 1st DMA transfer area, PU:0x00000000 */
85 …REQ_SUSPECTED_66200 0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
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/linux-6.12.1/include/asm-generic/ !
Dhyperv-tlfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
17 * While not explicitly listed in the TLFS, Hyper-V always runs with a page size
18 * of 4096. These definitions are used when communicating with Hyper-V using
23 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
24 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
27 * Hyper-V provides two categories of flags relevant to guest VMs. The
29 * to guests on this particular instance of Hyper-V. The "Features"
35 * architecture specific portion of hyperv-tlfs.h. Some of these flags exist
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/linux-6.12.1/crypto/ !
Ddh.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Diffie-Hellman Key Agreement Method [RFC2631]
24 mpi_free(ctx->p); in dh_clear_ctx()
25 mpi_free(ctx->g); in dh_clear_ctx()
26 mpi_free(ctx->xa); in dh_clear_ctx()
32 * ya = g^xa mod p; [RFC2631 sec 2.1.1]
34 * ZZ = yb^xa mod p; [RFC2631 sec 2.1.1]
39 return mpi_powm(val, base, ctx->xa, ctx->p); in _compute_val()
50 return (p_len < 2048) ? -EINVAL : 0; in dh_check_params_length()
52 return (p_len < 1536) ? -EINVAL : 0; in dh_check_params_length()
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/linux-6.12.1/sound/soc/tegra/ !
Dtegra210_i2s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra210_i2s.h - Definitions for Tegra210 I2S driver
34 #define TEGRA210_I2S_TX_CTRL 0x64
50 /* Bit fields, shifts and masks */
55 #define I2S_EN_MASK BIT(I2S_EN_SHIFT)
56 #define I2S_EN BIT(I2S_EN_SHIFT)
62 #define I2S_NEG_EDGE 1
64 #define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)
69 #define I2S_FMT_FSYNC 1
76 #define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)
[all …]
Dtegra210_sfc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra210_sfc.h - Definitions for Tegra210 SFC driver
5 * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
34 #define TEGRA210_SFC_TX_FREQ 0x64
48 #define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
53 #define TEGRA210_SFC_COEF_RAM_EN BIT(0)
55 #define TEGRA210_SFC_SOFT_RESET_EN BIT(0)
59 #define TEGRA210_SFC_RAM_CTRL_RW_WRITE (1 << 14)
60 #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN (1 << 13)
61 #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12)

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