Lines Matching +full:1 +full:x64 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author:Mark Yao <mark.yao@rock-chips.com>
14 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
16 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
17 #define VOP2_FEATURE_HAS_VO0_GRF BIT(1)
18 #define VOP2_FEATURE_HAS_VO1_GRF BIT(2)
19 #define VOP2_FEATURE_HAS_VOP_GRF BIT(3)
20 #define VOP2_FEATURE_HAS_SYS_PMU BIT(4)
22 #define WIN_FEATURE_AFBDC BIT(0)
23 #define WIN_FEATURE_CLUSTER BIT(1)
52 #define VOP2_PD_CLUSTER0 BIT(0)
53 #define VOP2_PD_CLUSTER1 BIT(1)
54 #define VOP2_PD_CLUSTER2 BIT(2)
55 #define VOP2_PD_CLUSTER3 BIT(3)
56 #define VOP2_PD_DSC_8K BIT(5)
57 #define VOP2_PD_DSC_4K BIT(6)
58 #define VOP2_PD_ESMART BIT(7)
171 #define FS_NEW_INTR BIT(4)
172 #define ADDR_SAME_INTR BIT(5)
173 #define LINE_FLAG1_INTR BIT(6)
174 #define WIN0_EMPTY_INTR BIT(7)
175 #define WIN1_EMPTY_INTR BIT(8)
176 #define WIN2_EMPTY_INTR BIT(9)
177 #define WIN3_EMPTY_INTR BIT(10)
178 #define HWC_EMPTY_INTR BIT(11)
179 #define POST_BUF_EMPTY_INTR BIT(12)
180 #define PWM_GEN_INTR BIT(13)
181 #define DMA_FINISH_INTR BIT(14)
182 #define FS_FIELD_INTR BIT(15)
183 #define FE_INTR BIT(16)
184 #define WB_UV_FIFO_FULL_INTR BIT(17)
185 #define WB_YRGB_FIFO_FULL_INTR BIT(18)
186 #define WB_COMPLETE_INTR BIT(19)
273 #define RK3568_VP_BCSH_BCS 0x64
324 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
352 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
394 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15)
396 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31)
397 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20)
399 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17)
400 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16)
401 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15)
402 #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10)
403 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9)
404 #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8)
405 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7)
406 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6)
407 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5)
408 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4)
412 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)
414 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1)
415 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
418 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24)
420 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20)
426 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5)
427 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4)
428 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3)
429 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1)
430 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
439 #define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7)
440 #define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6)
441 #define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5)
442 #define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4)
443 #define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3)
444 #define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2)
445 #define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1)
446 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0)
463 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5)
464 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4)
466 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31)
468 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28)
474 #define VOP2_COLOR_KEY_MASK BIT(31)
476 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28)
477 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp)
502 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0)
504 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0)
511 #define VP_INT_DSP_HOLD_VALID BIT(6)
512 #define VP_INT_FS_FIELD BIT(5)
513 #define VP_INT_POST_BUF_EMPTY BIT(4)
514 #define VP_INT_LINE_FLAG1 BIT(3)
515 #define VP_INT_LINE_FLAG0 BIT(2)
516 #define VOP2_INT_BUS_ERRPR BIT(1)
517 #define VP_INT_FS BIT(0)
519 #define POLFLAG_DCLK_INV BIT(3)
532 ROCKCHIP_VOP2_PHY_ID_INVALID = -1,