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/linux-6.12.1/Documentation/i2c/
Dten-bit-addresses.rst2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
17 The current 10 bit address support is minimal. It should work, however
[all …]
/linux-6.12.1/Documentation/gpu/
Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
111 Cross-device interoperability
115 canonical formats for use between AFBC-enabled devices. Formats which
119 .. flat-table:: AFBC formats
121 * - Fourcc code
122 - Description
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/linux-6.12.1/scripts/gdb/linux/
Dpgtable.py1 # SPDX-License-Identifier: GPL-2.0-only
44 return (bit_start, bit_end), data >> bit_start & ((1 << (1 + bit_end - bit_start)) - 1)
82 ---
83 …{'bit' : <4} {self.page_level_write_through[0]: <10} {'page level write through': <30} {self.page_…
84 …{'bit' : <4} {self.page_level_cache_disabled[0]: <10} {'page level cache disabled': <30} {self.pag…
140 next_level = self.page_hierarchy_level - 1
150 ---
155 return "" if level == 1 else f"{'bit': <3} {ps_bit: <5} {'page size': <30} {ps}"
163 ---
164 {'bit': <4} {self.entry_present[0]: <10} {'entry present': <30} {self.entry_present[1]}
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Dni_at_ao.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
[all …]
/linux-6.12.1/drivers/net/wireless/ath/wil6210/
Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
/linux-6.12.1/drivers/net/ethernet/asix/
Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
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/linux-6.12.1/drivers/net/ethernet/dec/tulip/
Dpnic2.c5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
30 * Bit 11:10 - Loop Back Operation Mode
31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
[all …]
/linux-6.12.1/drivers/iio/imu/bmi323/
Dbmi323.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * IIO driver for Bosch BMI323 6-Axis IMU
25 #define BMI323_STATUS_POR_MSK BIT(0)
36 #define BMI323_STATUS_NOMOTION_MSK BIT(0)
37 #define BMI323_STATUS_MOTION_MSK BIT(1)
38 #define BMI323_STATUS_STP_WTR_MSK BIT(5)
39 #define BMI323_STATUS_TAP_MSK BIT(8)
40 #define BMI323_STATUS_ERROR_MSK BIT(10)
41 #define BMI323_STATUS_TMP_DRDY_MSK BIT(11)
42 #define BMI323_STATUS_GYR_DRDY_MSK BIT(12)
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/
Dcss_receiver_2400_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
Disp_acquisition_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
22 /* --------------------------------------------------*/
26 /* --------------------------------------------------*/
28 /* --------------------------------------------------*/
32 /* --------------------------------------------------*/
34 /* --------------------------------------------------*/
49 #define ACQ_FSM_STATE_INFO_REG_ID 10
80 /* bit definitions */
88 /* --------------------------------------------------*/
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/linux-6.12.1/drivers/staging/media/atomisp/pci/css_2401_system/hrt/
Dmipi_backend_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
/linux-6.12.1/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
39 #define MDIO_CTRL2 7 /* 10G control 2 */
40 #define MDIO_STAT2 8 /* 10G status 2 */
41 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
42 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
43 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
[all …]
/linux-6.12.1/sound/soc/codecs/
Dmt6357.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt6357.h -- mt6357 ALSA SoC audio codec driver
14 /* Reg bit defines */
16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
[all …]
/linux-6.12.1/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-ath79/
Dar71xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)
173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)
174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)
[all …]
/linux-6.12.1/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
72 #define MT_TXD2_HTC_VLD BIT(13)
[all …]
Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
[all …]
/linux-6.12.1/drivers/phy/samsung/
Dphy-exynos4x12-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
20 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
21 #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
22 #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
23 #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
30 #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
31 #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
32 #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
[all …]
/linux-6.12.1/sound/firewire/oxfw/
Doxfw-command.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * oxfw_command.c - a part of driver for OXFW970/971 based devices
16 buf = kmalloc(len + 10, GFP_KERNEL); in avc_stream_set_format()
18 return -ENOMEM; in avc_stream_set_format()
30 memcpy(buf + 10, format, len); in avc_stream_set_format()
32 /* do transaction and check buf[1-8] are the same against command */ in avc_stream_set_format()
33 err = fcp_avc_transaction(unit, buf, len + 10, buf, len + 10, in avc_stream_set_format()
34 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_stream_set_format()
35 BIT(6) | BIT(7) | BIT(8)); in avc_stream_set_format()
38 else if (err < len + 10) in avc_stream_set_format()
[all …]
/linux-6.12.1/drivers/gpu/drm/mcde/
Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
[all …]
/linux-6.12.1/drivers/gpu/drm/mxsfb/
Dlcdif_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define CTRL_SFTRST BIT(31)
40 #define CTRL_CLKGATE BIT(30)
41 #define CTRL_BYPASS_COUNT BIT(19)
42 #define CTRL_VSYNC_MODE BIT(18)
43 #define CTRL_DOTCLK_MODE BIT(17)
44 #define CTRL_DATA_SELECT BIT(16)
45 #define CTRL_BUS_WIDTH_16 (0 << 10)
46 #define CTRL_BUS_WIDTH_8 (1 << 10)
47 #define CTRL_BUS_WIDTH_18 (2 << 10)
[all …]
/linux-6.12.1/include/linux/soc/mediatek/
Dinfracfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
9 #define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
10 #define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
11 #define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
12 #define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
13 #define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
14 #define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
15 #define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
16 #define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
[all …]
/linux-6.12.1/drivers/gpu/drm/vc4/
Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
[all …]

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