Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
20 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
21 #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
22 #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
23 #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
30 #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
31 #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
32 #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
38 #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9)
39 #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10)
40 #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11)
46 #define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND BIT(12)
47 #define EXYNOS_4x12_UPHYPWR_HSIC1_PWR BIT(13)
48 #define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP BIT(14)
69 #define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3)
70 #define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4)
71 #define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7)
73 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
74 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_OFFSET 10
75 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
76 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
77 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
78 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
79 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
84 #define EXYNOS_4x12_URSTCON_PHY0 BIT(0)
85 #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1)
86 #define EXYNOS_4x12_URSTCON_OTG_PHYLINK BIT(2)
87 #define EXYNOS_4x12_URSTCON_HOST_PHY BIT(3)
88 /* The following bit defines are presented in the
95 * The following bit values were chaned accordingly to the
98 #define EXYNOS_4x12_URSTCON_PHY1 BIT(4)
99 #define EXYNOS_4x12_URSTCON_HSIC0 BIT(6)
100 #define EXYNOS_4x12_URSTCON_HSIC1 BIT(5)
101 #define EXYNOS_4x12_URSTCON_HOST_LINK_ALL BIT(7)
102 #define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10)
103 #define EXYNOS_4x12_URSTCON_HOST_LINK_P1 BIT(9)
104 #define EXYNOS_4x12_URSTCON_HOST_LINK_P2 BIT(8)
108 #define EXYNOS_4x12_USB_ISOL_OTG BIT(0)
110 #define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0)
112 #define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0)
114 /* Mode switching SUB Device <-> Host */
140 case 10 * MHZ: in exynos4x12_rate_to_clk()
159 return -EINVAL; in exynos4x12_rate_to_clk()
167 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_isol()
171 switch (inst->cfg->id) { in exynos4x12_isol()
189 regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); in exynos4x12_isol()
194 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_setup_clk()
197 clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK); in exynos4x12_setup_clk()
200 if (drv->cfg->has_refclk_sel) in exynos4x12_setup_clk()
203 clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET; in exynos4x12_setup_clk()
205 writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK); in exynos4x12_setup_clk()
210 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_phy_pwr()
216 switch (inst->cfg->id) { in exynos4x12_phy_pwr()
240 pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
242 writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
244 rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST); in exynos4x12_phy_pwr()
246 writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST); in exynos4x12_phy_pwr()
247 udelay(10); in exynos4x12_phy_pwr()
249 writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST); in exynos4x12_phy_pwr()
254 pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
256 writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
262 if (inst->int_cnt++ > 0) in exynos4x12_power_on_int()
272 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_power_on()
274 if (inst->ext_cnt++ > 0) in exynos4x12_power_on()
277 if (inst->cfg->id == EXYNOS4x12_HOST) { in exynos4x12_power_on()
278 regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, in exynos4x12_power_on()
281 exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_on()
284 if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) in exynos4x12_power_on()
285 regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, in exynos4x12_power_on()
289 if (inst->cfg->id == EXYNOS4x12_HSIC0 || in exynos4x12_power_on()
290 inst->cfg->id == EXYNOS4x12_HSIC1) { in exynos4x12_power_on()
291 exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_on()
292 exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_HOST]); in exynos4x12_power_on()
302 if (inst->int_cnt-- > 1) in exynos4x12_power_off_int()
311 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_power_off()
313 if (inst->ext_cnt-- > 1) in exynos4x12_power_off()
316 if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) in exynos4x12_power_off()
317 regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, in exynos4x12_power_off()
321 if (inst->cfg->id == EXYNOS4x12_HOST) in exynos4x12_power_off()
322 exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_off()
324 if (inst->cfg->id == EXYNOS4x12_HSIC0 || in exynos4x12_power_off()
325 inst->cfg->id == EXYNOS4x12_HSIC1) { in exynos4x12_power_off()
326 exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_off()
327 exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_HOST]); in exynos4x12_power_off()