/linux-6.12.1/Documentation/devicetree/bindings/mtd/ |
D | arm,pl353-nand-r2p1.yaml | 37 reg = <0xe000e000 0x0001000>; 40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 46 nfc0: nand-controller@0,0 { 48 reg = <0 0 0x1000000>; 50 #size-cells = <0>;
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D | intel,lgm-ebunand.yaml | 48 minimum: 0 70 reg = <0xe0f00000 0x100>, 71 <0xe1000000 0x300>, 72 <0xe1400000 0x8000>, 73 <0xe1c00000 0x1000>, 74 <0x17400000 0x4>, 75 <0x17c00000 0x4>; 82 #size-cells = <0>; 84 nand@0 { 85 reg = <0>;
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/linux-6.12.1/tools/testing/selftests/arm64/fp/ |
D | sme-inst.h | 12 .inst 0x4bf5800 \ 33 .macro _ldr_za nw, nxbase, offset=0 34 .inst 0xe1000000 \ 44 .macro _str_za nw, nxbase, offset=0 45 .inst 0xe1200000 \ 57 .inst 0xe11f8000 \ 58 | (((\nx) & 0x1f) << 5) 67 .inst 0xe13f8000 \ 68 | (((\nx) & 0x1f) << 5)
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/linux-6.12.1/include/video/ |
D | cvisionppc.h | 27 #define CSPPC_PCI_BRIDGE 0xfffe0000 28 #define CSPPC_BRIDGE_ENDIAN 0x0000 29 #define CSPPC_BRIDGE_INT 0x0010 31 #define CVPPC_PCI_CONFIG 0xfffc0000 32 #define CVPPC_ROM_ADDRESS 0xe2000001 33 #define CVPPC_REGS_REGION 0xef000000 34 #define CVPPC_FB_APERTURE_ONE 0xe0000000 35 #define CVPPC_FB_APERTURE_TWO 0xe1000000 36 #define CVPPC_FB_SIZE 0x00800000 37 #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */ [all …]
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
D | mpc8544ds.dts | 16 reg = <0 0 0 0>; // Filled by U-Boot 20 reg = <0 0xe0005000 0 0x1000>; 22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>; 26 ranges = <0x0 0x0 0xe0000000 0x100000>; 30 reg = <0 0xe0008000 0 0x1000>; 31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>; 34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 37 /* IDSEL 0x11 J17 Slot 1 */ 38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
D | arm,pl35x-smc.yaml | 33 pattern: "^memory-controller@[0-9a-f]+$" 69 - description: Combined or Memory interface 0 IRQ 73 "@[0-7],[a-f0-9]+$": 91 minimum: 0 141 reg = <0xe000e000 0x0001000>; 144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 150 nfc0: nand-controller@0,0 { 152 reg = <0 0 0x1000000>; [all …]
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/linux-6.12.1/arch/arm/mach-omap1/ |
D | hardware.h | 53 ? OMAP_CS3_PHYS : 0; in omap_cs0m_phys() 59 ? 0 : OMAP_CS3_PHYS; in omap_cs3_phys() 64 #define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */ 82 #define OMAP_MPU_TIMER1_BASE (0xfffec500) 83 #define OMAP_MPU_TIMER2_BASE (0xfffec600) 84 #define OMAP_MPU_TIMER3_BASE (0xfffec700) 88 #define MPU_TIMER_ST (1 << 0) 97 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) 98 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) 99 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) [all …]
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/linux-6.12.1/arch/arm64/boot/dts/qcom/ |
D | qcm6490-shift-otter.dts | 44 reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>; 56 pinctrl-0 = <&volume_down_default>; 71 #size-cells = <0>; 73 connector@0 { 75 reg = <0>; 81 #size-cells = <0>; 83 port@0 { 84 reg = <0>; 112 reg = <0x0 0xe1000000 0x0 0x2300000>; 117 reg = <0x0 0x88f00000 0x0 0x1e00000>; [all …]
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D | sm8350-sony-xperia-sagami.dtsi | 33 reg = <0 0xe1000000 0 0x2300000>; 53 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>; 94 reg = <0 0xe1000000 0 0x2300000>; 100 reg = <0 0xffc00000 0 0x100000>; 101 console-size = <0x40000>; 102 record-size = <0x1000>; 124 regulators-0 { 496 reg = <0x40>; 511 reg = <0x41>; 592 power-source = <0>; [all …]
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D | qcm6490-fairphone-fp5.dts | 42 reg = <0x0 0xe1000000 0x0 (2700 * 1224 * 4)>; 54 pinctrl-0 = <&volume_down_default>, <&hall_sensor_default>; 78 #size-cells = <0>; 82 connector@0 { 84 reg = <0>; 90 #size-cells = <0>; 92 port@0 { 93 reg = <0>; 113 reg = <0x0 0xe1000000 0x0 0x2300000>; 118 reg = <0x0 0x88f00000 0x0 0x1e00000>; [all …]
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D | x1e80100.dtsi | 36 #clock-cells = <0>; 42 #clock-cells = <0>; 47 #clock-cells = <0>; 56 #clock-cells = <0>; 66 #size-cells = <0>; 68 CPU0: cpu@0 { 71 reg = <0x0 0x0>; 88 reg = <0x0 0x100>; 99 reg = <0x0 0x200>; 110 reg = <0x0 0x300>; [all …]
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/linux-6.12.1/arch/powerpc/boot/dts/ |
D | currituck.dts | 13 /memreserve/ 0x01f00000 0x00100000; // spin table 20 dcr-parent = <&{/cpus/cpu@0}>; 28 #size-cells = <0>; 30 cpu@0 { 33 reg = <0>; 58 cpu-release-addr = <0x0 0x01f00000>; 64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage 70 dcr-reg = <0xffc00000 0x00040000>; 71 #address-cells = <0>; 72 #size-cells = <0>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/amd/ |
D | amd-seattle-soc.dtsi | 20 reg = <0x0 0xe1110000 0 0x1000>, 21 <0x0 0xe112f000 0 0x2000>, 22 <0x0 0xe1140000 0 0x2000>, 23 <0x0 0xe1160000 0 0x2000>; 24 interrupts = <1 9 0xf04>; 25 ranges = <0 0 0 0xe1100000 0 0x100000>; 29 reg = <0x0 0x00080000 0 0x1000>; 35 interrupts = <1 13 0xff04>, 36 <1 14 0xff04>, 37 <1 11 0xff04>, [all …]
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/linux-6.12.1/arch/arm64/include/asm/ |
D | fpsimdmacros.h | 12 stp q0, q1, [\state, #16 * 0] 48 ldp q0, q1, [\state, #16 * 0] 73 .if (\nr) < 0 || (\nr) > 30 79 .if (\znr) < 0 || (\znr) > 31 85 .if (\pnr) < 0 || (\pnr) > 15 106 .macro _sve_str_v nz, nxbase, offset=0 109 _check_num (\offset), -0x100, 0xff 110 .inst 0xe5804000 \ 114 | (((\offset) & 0x1f8) << 13) 118 .macro _sve_ldr_v nz, nxbase, offset=0 [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/ |
D | lpc32xx.dtsi | 20 #size-cells = <0>; 22 cpu@0 { 25 reg = <0x0>; 32 #clock-cells = <0>; 39 #clock-cells = <0>; 49 ranges = <0x00000000 0x00000000 0x10000000>, 50 <0x20000000 0x20000000 0x30000000>, 51 <0xe0000000 0xe0000000 0x04000000>; 55 reg = <0x08000000 0x20000>; 59 ranges = <0x00000000 0x08000000 0x20000>; [all …]
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/linux-6.12.1/tools/testing/selftests/arm64/abi/ |
D | syscall-abi-asm.S | 11 // x0: SVE VL, 0 for FP only 33 .macro _ldr_za nw, nxbase, offset=0 34 .inst 0xe1000000 \ 44 .macro _str_za nw, nxbase, offset=0 45 .inst 0xe1200000 \ 57 .inst 0xe11f8000 \ 58 | (((\nx) & 0x1f) << 5) 67 .inst 0xe13f8000 \ 68 | (((\nx) & 0x1f) << 5) 92 mov w12, #0 [all …]
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/linux-6.12.1/arch/arm/boot/dts/xilinx/ |
D | zynq-7000.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 18 reg = <0>; 47 interrupts = <0 5 4>, <0 6 4>; 49 reg = <0xf8891000 0x1000>, 50 <0xf8893000 0x1000>; 69 #size-cells = <0>; 72 port@0 { 73 reg = <0>; 104 reg = <0xf8007100 0x20>; [all …]
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/linux-6.12.1/arch/arm/mach-lpc32xx/ |
D | lpc32xx.h | 17 * AHB 0 physical base addresses 19 #define LPC32XX_SLC_BASE 0x20020000 20 #define LPC32XX_SSP0_BASE 0x20084000 21 #define LPC32XX_SPI1_BASE 0x20088000 22 #define LPC32XX_SSP1_BASE 0x2008C000 23 #define LPC32XX_SPI2_BASE 0x20090000 24 #define LPC32XX_I2S0_BASE 0x20094000 25 #define LPC32XX_SD_BASE 0x20098000 26 #define LPC32XX_I2S1_BASE 0x2009C000 27 #define LPC32XX_MLC_BASE 0x200A8000 [all …]
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/linux-6.12.1/crypto/ |
D | aes_generic.c | 67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6, 68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591, 69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56, 70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec, 71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa, 72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb, 73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45, 74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b, 75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c, 76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83, [all …]
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/linux-6.12.1/arch/arm/boot/dts/microchip/ |
D | sama7g5.dtsi | 31 #size-cells = <0>; 33 cpu0: cpu@0 { 36 reg = <0x0>; 88 hysteresis = <0>; 94 hysteresis = <0>; 100 hysteresis = <0>; 122 #clock-cells = <0>; 127 #clock-cells = <0>; 132 #clock-cells = <0>; 151 reg = <0x100000 0x20000>; [all …]
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/linux-6.12.1/drivers/scsi/sym53c8xx_2/ |
D | sym_defs.h | 45 #define FE_LED0 (1<<0) 88 #define ISCON 0x10 /* connected to scsi */ 89 #define CRST 0x08 /* force reset */ 90 #define IARB 0x02 /* immediate arbitration */ 93 #define SDU 0x80 /* cmd: disconnect will raise error */ 94 #define CHM 0x40 /* sta: chained mode */ 95 #define WSS 0x08 /* sta: wide scsi send [W]*/ 96 #define WSR 0x01 /* sta: wide scsi received [W]*/ 99 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 100 #define ULTRA 0x80 /* cmd: ULTRA enable */ [all …]
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/linux-6.12.1/drivers/net/ethernet/dec/tulip/ |
D | uli526x.c | 39 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ 40 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ 42 #define ULI526X_IO_SIZE 0x100 43 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ 44 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ 48 #define TX_BUF_ALLOC 0x600 49 #define RX_ALLOC_SIZE 0x620 51 #define CR0_DEFAULT 0 52 #define CR6_DEFAULT 0x22200000 53 #define CR7_DEFAULT 0x180c1 [all …]
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D | dmfe.c | 22 Removed IRQ 0-15 assumption 92 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */ 93 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */ 94 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */ 95 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */ 97 #define DM9102_IO_SIZE 0x80 98 #define DM9102A_IO_SIZE 0x100 99 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */ 100 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */ 101 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */ [all …]
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/linux-6.12.1/drivers/scsi/ |
D | ncr53c8xx.h | 72 * bit 0 : all features enabled, except: 107 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0) 128 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0 146 #define SCSI_NCR_SETUP_DISCONNECTION (0) 157 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0) 164 #define SCSI_NCR_SETUP_MASTER_PARITY (0) 173 #define SCSI_NCR_SETUP_SCSI_PARITY (0) 410 …np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0) 446 } while (0) 452 } while (0) [all …]
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/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/ |
D | bnx2x_hsi.h | 17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 42 #define PIN_CFG_NA 0x00000000 43 #define PIN_CFG_GPIO0_P0 0x00000001 44 #define PIN_CFG_GPIO1_P0 0x00000002 [all …]
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