Lines Matching +full:0 +full:xe1000000
39 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
40 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
42 #define ULI526X_IO_SIZE 0x100
43 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
44 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
48 #define TX_BUF_ALLOC 0x600
49 #define RX_ALLOC_SIZE 0x620
51 #define CR0_DEFAULT 0
52 #define CR6_DEFAULT 0x22200000
53 #define CR7_DEFAULT 0x180c1
54 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
55 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
59 #define MAX_CHECK_PACKET 0x8000
61 #define ULI526X_10MHF 0
67 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
68 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
69 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
70 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
71 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
72 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
82 } while (0)
91 #define CR9_SROM_READ 0x4800
92 #define CR9_SRCS 0x1
93 #define CR9_SRCLK 0x2
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
101 #define PHY_POWER_DOWN 0x800
103 #define SROM_V41_CODE 0x14
184 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
185 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
186 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
187 DCR15 = 0x78
191 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
192 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
193 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
278 ULI526X_DBUG(0, "uli526x_init_one()", 0); in uli526x_init_one()
297 if (!pci_resource_start(pdev, 0)) { in uli526x_init_one()
303 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { in uli526x_init_one()
310 if (err < 0) { in uli526x_init_one()
322 sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, in uli526x_init_one()
350 ioaddr = pci_iomap(pdev, 0, 0); in uli526x_init_one()
368 for (i = 0; i < 64; i++) in uli526x_init_one()
372 …if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC add… in uli526x_init_one()
374 uw32(DCR0, 0x10000); //Diagnosis mode in uli526x_init_one()
375 uw32(DCR13, 0x1c0); //Reset dianostic pointer port in uli526x_init_one()
376 uw32(DCR14, 0); //Clear reset port in uli526x_init_one()
377 uw32(DCR14, 0x10); //Reset ID Table pointer in uli526x_init_one()
378 uw32(DCR14, 0); //Clear reset port in uli526x_init_one()
379 uw32(DCR13, 0); //Clear CR13 in uli526x_init_one()
380 uw32(DCR13, 0x1b0); //Select ID Table access port in uli526x_init_one()
382 for (i = 0; i < 6; i++) in uli526x_init_one()
385 uw32(DCR13, 0); //Clear CR13 in uli526x_init_one()
386 uw32(DCR0, 0); //Clear CR0 in uli526x_init_one()
391 for (i = 0; i < 6; i++) in uli526x_init_one()
406 return 0; in uli526x_init_one()
415 sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, in uli526x_init_one()
436 sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, in uli526x_remove_one()
456 ULI526X_DBUG(0, "uli526x_open", 0); in uli526x_open()
460 db->tx_packet_cnt = 0; in uli526x_open()
461 db->rx_avail_cnt = 0; in uli526x_open()
464 db->wait_reset = 0; in uli526x_open()
466 db->NIC_capability = 0xf; /* All capability*/ in uli526x_open()
467 db->PHY_reg4 = 0x1e0; in uli526x_open()
485 timer_setup(&db->timer, uli526x_timer, 0); in uli526x_open()
489 return 0; in uli526x_open()
510 ULI526X_DBUG(0, "uli526x_init()", 0); in uli526x_init()
520 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) { in uli526x_init()
524 if (phy_value != 0xffff && phy_value != 0) { in uli526x_init()
536 phy_reg_reset = phy->read(db, db->phy_addr, 0); in uli526x_init()
537 phy_reg_reset = (phy_reg_reset | 0x8000); in uli526x_init()
538 phy->write(db, db->phy_addr, 0, phy_reg_reset); in uli526x_init()
545 while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000) in uli526x_init()
590 ULI526X_DBUG(0, "uli526x_start_xmit", 0); in uli526x_start_xmit()
612 uw32(DCR7, 0); in uli526x_start_xmit()
617 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); in uli526x_start_xmit()
624 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ in uli526x_start_xmit()
626 uw32(DCR1, 0x1); /* Issue Tx polling */ in uli526x_start_xmit()
664 db->phy.write(db, db->phy_addr, 0, 0x8000); in uli526x_stop()
672 return 0; in uli526x_stop()
689 uw32(DCR7, 0); in uli526x_interrupt()
694 if ( !(db->cr5_data & 0x180c1) ) { in uli526x_interrupt()
702 if (db->cr5_data & 0x2000) { in uli526x_interrupt()
712 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) in uli526x_interrupt()
720 if ( db->cr5_data & 0x01) in uli526x_interrupt()
753 if (tdes0 & 0x80000000) in uli526x_free_tx_pkt()
761 if ( tdes0 != 0x7fffffff ) { in uli526x_free_tx_pkt()
762 dev->stats.collisions += (tdes0 >> 3) & 0xf; in uli526x_free_tx_pkt()
763 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; in uli526x_free_tx_pkt()
766 if (tdes0 & 0x0002) { /* UnderRun */ in uli526x_free_tx_pkt()
773 if (tdes0 & 0x0100) in uli526x_free_tx_pkt()
775 if (tdes0 & 0x0200) in uli526x_free_tx_pkt()
777 if (tdes0 & 0x0400) in uli526x_free_tx_pkt()
779 if (tdes0 & 0x0800) in uli526x_free_tx_pkt()
781 if (tdes0 & 0x4000) in uli526x_free_tx_pkt()
813 if (rdes0 & 0x80000000) /* packet owner check */ in uli526x_rx_packet()
823 if ( (rdes0 & 0x300) != 0x300) { in uli526x_rx_packet()
826 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); in uli526x_rx_packet()
830 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; in uli526x_rx_packet()
833 if (rdes0 & 0x8000) { in uli526x_rx_packet()
840 if (rdes0 & 0x80) in uli526x_rx_packet()
844 if ( !(rdes0 & 0x8000) || in uli526x_rx_packet()
871 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); in uli526x_rx_packet()
892 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); in uli526x_set_filter_mode()
896 ULI526X_DBUG(0, "Enable PROM Mode", 0); in uli526x_set_filter_mode()
905 ULI526X_DBUG(0, "Pass all multicast address", in uli526x_set_filter_mode()
913 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev)); in uli526x_set_filter_mode()
985 return 0; in netdev_get_link_ksettings()
992 return 0; in netdev_get_link()
1000 wol->wolopts = 0; in uli526x_get_wol()
1022 u8 tmp_cr12 = 0; in uli526x_timer()
1025 //ULI526X_DBUG(0, "uli526x_timer()", 0); in uli526x_timer()
1031 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { in uli526x_timer()
1035 db->interval_rx_cnt = 0; in uli526x_timer()
1040 uw32(DCR1, 0x1); // Tx polling again in uli526x_timer()
1051 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); in uli526x_timer()
1061 if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0) in uli526x_timer()
1064 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { in uli526x_timer()
1066 ULI526X_DBUG(0, "Link Failed", tmp_cr12); in uli526x_timer()
1073 if ( !(db->media_mode & 0x8) ) in uli526x_timer()
1074 phy->write(db, db->phy_addr, 0, 0x1000); in uli526x_timer()
1078 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ in uli526x_timer()
1082 if ((tmp_cr12 & 0x3) && db->link_failed) { in uli526x_timer()
1083 ULI526X_DBUG(0, "Link link OK", tmp_cr12); in uli526x_timer()
1084 db->link_failed = 0; in uli526x_timer()
1092 if(db->link_failed==0) in uli526x_timer()
1105 else if(!(tmp_cr12 & 0x3) && db->link_failed) in uli526x_timer()
1113 db->init = 0; in uli526x_timer()
1136 uw32(DCR7, 0); /* Disable Interrupt */ in uli526x_reset_prepare()
1146 db->tx_packet_cnt = 0; in uli526x_reset_prepare()
1147 db->rx_avail_cnt = 0; in uli526x_reset_prepare()
1150 db->wait_reset = 0; in uli526x_reset_prepare()
1164 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); in uli526x_dynamic_reset()
1183 ULI526X_DBUG(0, "uli526x_suspend", 0); in uli526x_suspend()
1186 return 0; in uli526x_suspend()
1191 device_set_wakeup_enable(dev_d, 0); in uli526x_suspend()
1193 return 0; in uli526x_suspend()
1204 ULI526X_DBUG(0, "uli526x_resume", 0); in uli526x_resume()
1208 return 0; in uli526x_resume()
1216 return 0; in uli526x_resume()
1225 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); in uli526x_free_rxbuffer()
1244 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { in uli526x_reuse_skb()
1249 rxptr->rdes0 = cpu_to_le32(0x80000000); in uli526x_reuse_skb()
1253 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); in uli526x_reuse_skb()
1272 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); in uli526x_descriptor_init()
1290 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { in uli526x_descriptor_init()
1292 tmp_tx->tdes0 = cpu_to_le32(0); in uli526x_descriptor_init()
1293 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ in uli526x_descriptor_init()
1306 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { in uli526x_descriptor_init()
1307 tmp_rx->rdes0 = cpu_to_le32(0); in uli526x_descriptor_init()
1308 tmp_rx->rdes1 = cpu_to_le32(0x01000600); in uli526x_descriptor_init()
1340 #define FLT_SHIFT 0
1353 ULI526X_DBUG(0, "send_filter_frame()", 0); in send_filter_frame()
1360 *suptr++ = addrptr[0] << FLT_SHIFT; in send_filter_frame()
1365 *suptr++ = 0xffff << FLT_SHIFT; in send_filter_frame()
1366 *suptr++ = 0xffff << FLT_SHIFT; in send_filter_frame()
1367 *suptr++ = 0xffff << FLT_SHIFT; in send_filter_frame()
1372 *suptr++ = addrptr[0] << FLT_SHIFT; in send_filter_frame()
1378 *suptr++ = 0xffff << FLT_SHIFT; in send_filter_frame()
1379 *suptr++ = 0xffff << FLT_SHIFT; in send_filter_frame()
1380 *suptr++ = 0xffff << FLT_SHIFT; in send_filter_frame()
1385 txptr->tdes1 = cpu_to_le32(0x890000c0); in send_filter_frame()
1391 txptr->tdes0 = cpu_to_le32(0x80000000); in send_filter_frame()
1392 update_cr6(db->cr6_data | 0x2000, ioaddr); in send_filter_frame()
1393 uw32(DCR1, 0x1); /* Issue Tx polling */ in send_filter_frame()
1422 rxptr->rdes0 = cpu_to_le32(0x80000000); in allocate_rx_buffer()
1438 u16 srom_data = 0; in read_srom_word()
1450 for (i = 5; i >= 0; i--) { in read_srom_word()
1457 for (i = 16; i > 0; i--) { in read_srom_word()
1461 ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0); in read_srom_word()
1478 u8 ErrFlag = 0; in uli526x_sense_speed()
1484 if ( (phy_mode & 0x24) == 0x24 ) { in uli526x_sense_speed()
1486 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7); in uli526x_sense_speed()
1487 if(phy_mode&0x8000) in uli526x_sense_speed()
1488 phy_mode = 0x8000; in uli526x_sense_speed()
1489 else if(phy_mode&0x4000) in uli526x_sense_speed()
1490 phy_mode = 0x4000; in uli526x_sense_speed()
1491 else if(phy_mode&0x2000) in uli526x_sense_speed()
1492 phy_mode = 0x2000; in uli526x_sense_speed()
1494 phy_mode = 0x1000; in uli526x_sense_speed()
1497 case 0x1000: db->op_mode = ULI526X_10MHF; break; in uli526x_sense_speed()
1498 case 0x2000: db->op_mode = ULI526X_10MFD; break; in uli526x_sense_speed()
1499 case 0x4000: db->op_mode = ULI526X_100MHF; break; in uli526x_sense_speed()
1500 case 0x8000: db->op_mode = ULI526X_100MFD; break; in uli526x_sense_speed()
1505 ULI526X_DBUG(0, "Link Failed :", phy_mode); in uli526x_sense_speed()
1525 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0; in uli526x_set_phyxcer()
1533 case ULI526X_10MHF: phy_reg |= 0x20; break; in uli526x_set_phyxcer()
1534 case ULI526X_10MFD: phy_reg |= 0x40; break; in uli526x_set_phyxcer()
1535 case ULI526X_100MHF: phy_reg |= 0x80; break; in uli526x_set_phyxcer()
1536 case ULI526X_100MFD: phy_reg |= 0x100; break; in uli526x_set_phyxcer()
1542 if ( !(phy_reg & 0x01e0)) { in uli526x_set_phyxcer()
1549 phy->write(db, db->phy_addr, 0, 0x1200); in uli526x_set_phyxcer()
1567 if (db->op_mode & 0x4) in uli526x_process_mode()
1575 if (!(db->media_mode & 0x8)) { in uli526x_process_mode()
1578 if (!(phy_reg & 0x1)) { in uli526x_process_mode()
1580 phy_reg = 0x0; in uli526x_process_mode()
1582 case ULI526X_10MHF: phy_reg = 0x0; break; in uli526x_process_mode()
1583 case ULI526X_10MFD: phy_reg = 0x100; break; in uli526x_process_mode()
1584 case ULI526X_100MHF: phy_reg = 0x2000; break; in uli526x_process_mode()
1585 case ULI526X_100MFD: phy_reg = 0x2100; break; in uli526x_process_mode()
1587 phy->write(db, db->phy_addr, 0, phy_reg); in uli526x_process_mode()
1600 for (i = 0; i < 35; i++) in phy_writeby_cr9()
1612 for (i = 0x10; i > 0; i = i >> 1) in phy_writeby_cr9()
1616 for (i = 0x10; i > 0; i = i >> 1) in phy_writeby_cr9()
1624 for (i = 0x8000; i > 0; i >>= 1) in phy_writeby_cr9()
1634 for (i = 0; i < 35; i++) in phy_readby_cr9()
1646 for (i = 0x10; i > 0; i = i >> 1) in phy_readby_cr9()
1650 for (i = 0x10; i > 0; i = i >> 1) in phy_readby_cr9()
1657 for (phy_data = 0, i = 0; i < 16; i++) { in phy_readby_cr9()
1672 cr10_value = (cr10_value << 16) + 0x08000000; in phy_readby_cr10()
1677 if (cr10_value & 0x10000000) in phy_readby_cr10()
1680 return cr10_value & 0x0ffff; in phy_readby_cr10()
1690 cr10_value = (cr10_value << 16) + 0x04000000 + phy_data; in phy_writeby_cr10()
1720 uw32(DCR9, 0x50000); in phy_read_1bit()
1722 phy_data = (ur32(DCR9) >> 19) & 0x1; in phy_read_1bit()
1723 uw32(DCR9, 0x40000); in phy_read_1bit()
1731 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1732 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1733 { 0, }
1752 module_param(mode, int, 0);
1753 module_param(cr6set, int, 0);
1754 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1755 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1765 ULI526X_DBUG(0, "init_module() ", debug); in uli526x_init_module()
1796 ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug); in uli526x_cleanup_module()