Lines Matching +full:0 +full:xe1000000
72 * bit 0 : all features enabled, except:
107 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
128 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
146 #define SCSI_NCR_SETUP_DISCONNECTION (0)
157 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
164 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
173 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
410 …np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
446 } while (0)
452 } while (0)
464 #define FE_LED0 (1<<0)
545 0, \
546 0, \
548 0, \
551 0x00, \
553 0, \
556 0, \
557 0, \
559 0, \
560 0, \
562 0x00 \
572 0, \
574 0, \
575 0, \
576 0, \
577 0, \
578 0, \
581 0, \
583 0x00, \
585 0, \
586 0, \
591 0, \
592 0, \
609 #define ISCON 0x10 /* connected to scsi */
610 #define CRST 0x08 /* force reset */
611 #define IARB 0x02 /* immediate arbitration */
614 #define SDU 0x80 /* cmd: disconnect will raise error */
615 #define CHM 0x40 /* sta: chained mode */
616 #define WSS 0x08 /* sta: wide scsi send [W]*/
617 #define WSR 0x01 /* sta: wide scsi received [W]*/
620 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
621 #define ULTRA 0x80 /* cmd: ULTRA enable */
622 /* bits 0-2, 7 rsvd for C1010 */
625 #define RRE 0x40 /* r/w:e enable response to resel. */
626 #define SRE 0x20 /* r/w:e enable response to select */
638 #define CREQ 0x80 /* r/w: SCSI-REQ */
639 #define CACK 0x40 /* r/w: SCSI-ACK */
640 #define CBSY 0x20 /* r/w: SCSI-BSY */
641 #define CSEL 0x10 /* r/w: SCSI-SEL */
642 #define CATN 0x08 /* r/w: SCSI-ATN */
643 #define CMSG 0x04 /* r/w: SCSI-MSG */
644 #define CC_D 0x02 /* r/w: SCSI-C_D */
645 #define CI_O 0x01 /* r/w: SCSI-I_O */
647 /*0a*/ u8 nc_ssid;
649 /*0b*/ u8 nc_sbcl;
651 /*0c*/ u8 nc_dstat;
652 #define DFE 0x80 /* sta: dma fifo empty */
653 #define MDPE 0x40 /* int: master data parity error */
654 #define BF 0x20 /* int: script: bus fault */
655 #define ABRT 0x10 /* int: script: command aborted */
656 #define SSI 0x08 /* int: script: single step */
657 #define SIR 0x04 /* int: script: interrupt instruct. */
658 #define IID 0x01 /* int: script: illegal instruct. */
660 /*0d*/ u8 nc_sstat0;
661 #define ILF 0x80 /* sta: data in SIDL register lsb */
662 #define ORF 0x40 /* sta: data in SODR register lsb */
663 #define OLF 0x20 /* sta: data in SODL register lsb */
664 #define AIP 0x10 /* sta: arbitration in progress */
665 #define LOA 0x08 /* sta: arbitration lost */
666 #define WOA 0x04 /* sta: arbitration won */
667 #define IRST 0x02 /* sta: scsi reset signal */
668 #define SDP 0x01 /* sta: scsi parity signal */
670 /*0e*/ u8 nc_sstat1;
671 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
673 /*0f*/ u8 nc_sstat2;
674 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
675 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
676 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
677 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
678 #define LDSC 0x02 /* sta: disconnect & reconnect */
686 #define CABRT 0x80 /* cmd: abort current operation */
687 #define SRST 0x40 /* mod: reset chip */
688 #define SIGP 0x20 /* r/w: message from host to ncr */
689 #define SEM 0x10 /* r/w: message between host + ncr */
690 #define CON 0x08 /* sta: connected to scsi */
691 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
692 #define SIP 0x02 /* sta: scsi-interrupt */
693 #define DIP 0x01 /* sta: host/script interrupt */
696 #define FLSH 0x04 /* sta: chip is flushing */
697 #define SRUN 0x02 /* sta: scripts are running */
698 #define SIRQD 0x01 /* r/w: disable INT pin */
704 #define EHP 0x04 /* 720 even host parity */
708 #define CSIGP 0x40
709 /* bits 0-2,7 rsvd for C1010 */
712 #define FLF 0x08 /* cmd: flush dma fifo */
713 #define CLF 0x04 /* cmd: clear dma fifo */
714 #define FM 0x02 /* mod: fetch pin mode */
715 #define WRIE 0x01 /* mod: write and invalidate enable */
722 #define MUX 0x80 /* 720 host bus multiplex mode */
723 #define BDIS 0x80 /* mod: burst disable */
724 #define MPEE 0x08 /* mod: master parity error enable */
727 #define DFS 0x20 /* mod: dma fifo size */
728 /* bits 0-1, 3-7 rsvd for C1010 */
742 #define BL_2 0x80 /* mod: burst length shift value +2 */
743 #define BL_1 0x40 /* mod: burst length shift value +1 */
744 #define ERL 0x08 /* mod: enable read line */
745 #define ERMP 0x04 /* mod: enable read multiple */
746 #define BOF 0x02 /* mod: burst op code fetch */
752 #define CLSE 0x80 /* mod: cache line size enable */
753 #define PFF 0x40 /* cmd: pre-fetch flush */
754 #define PFEN 0x20 /* mod: pre-fetch enable */
755 #define EA 0x20 /* mod: 720 enable-ack */
756 #define SSM 0x10 /* mod: single step mode */
757 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
758 #define STD 0x04 /* cmd: start dma mode */
759 #define IRQD 0x02 /* mod: irq disable */
760 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
761 /* bits 0-1 rsvd for C1010 */
767 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
768 #define STO 0x0400/* sta: timeout (select) */
769 #define GEN 0x0200/* sta: timeout (general) */
770 #define HTH 0x0100/* sta: timeout (handshake) */
771 #define MA 0x80 /* sta: phase mismatch */
772 #define CMP 0x40 /* sta: arbitration complete */
773 #define SEL 0x20 /* sta: selected by another device */
774 #define RSL 0x10 /* sta: reselected by another device*/
775 #define SGE 0x08 /* sta: gross error (over/underflow)*/
776 #define UDC 0x04 /* sta: unexpected disconnect */
777 #define RST 0x02 /* sta: scsi bus reset detected */
778 #define PAR 0x01 /* sta: scsi parity error */
791 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
792 #define DBLEN 0x08 /* clock doubler running */
793 #define DBLSEL 0x04 /* clock doubler selected */
797 #define ROF 0x40 /* reset scsi offset (after gross error!) */
798 #define DIF 0x20 /* 720 SCSI differential mode */
799 #define EXT 0x02 /* extended filtering */
802 #define TE 0x80 /* c: tolerAnt enable */
803 #define HSC 0x20 /* c: Halt SCSI Clock */
804 #define CSF 0x02 /* c: clear scsi fifo */
808 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
809 #define SMODE_HVD 0x40 /* High Voltage Differential */
810 #define SMODE_SE 0x80 /* Single Ended */
811 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
812 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
813 /* bits 0-5 rsvd for C1010 */
817 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
818 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
819 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
820 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
821 #define DISFC 0x10 /* Disable Auto FIFO Clear */
822 #define DILS 0x02 /* Disable Internal Load/Store */
823 #define DPR 0x01 /* Disable Pipe Req */
826 #define ZMOD 0x80 /* High Impedance Mode */
827 #define DIC 0x10 /* Disable Internal Cycles */
828 #define DDAC 0x08 /* Disable Dual Address Cycle */
829 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
830 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
831 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
850 #define U3EN 0x80 /* Enable Ultra 3 */
851 #define AIPEN 0x40 /* Allow check upper byte lanes */
852 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
854 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
882 #define SNDCRC 0x10 /* Send CRC Request */
912 #define SCR_DATA_OUT 0x00000000
913 #define SCR_DATA_IN 0x01000000
914 #define SCR_COMMAND 0x02000000
915 #define SCR_STATUS 0x03000000
916 #define SCR_DT_DATA_OUT 0x04000000
917 #define SCR_DT_DATA_IN 0x05000000
918 #define SCR_MSG_OUT 0x06000000
919 #define SCR_MSG_IN 0x07000000
921 #define SCR_ILG_OUT 0x04000000
922 #define SCR_ILG_IN 0x05000000
942 #define OPC_MOVE 0x08000000
944 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
945 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
946 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
948 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
949 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
950 #define SCR_CHMOV_TBL (0x10000000)
963 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
972 #define SCR_SEL_ABS 0x40000000
973 #define SCR_SEL_ABS_ATN 0x41000000
974 #define SCR_SEL_TBL 0x42000000
975 #define SCR_SEL_TBL_ATN 0x43000000
994 #define SCR_JMP_REL 0x04000000
1012 #define SCR_WAIT_DISC 0x48000000
1013 #define SCR_WAIT_RESEL 0x50000000
1028 #define SCR_SET(f) (0x58000000 | (f))
1029 #define SCR_CLR(f) (0x60000000 | (f))
1031 #define SCR_CARRY 0x00000400
1032 #define SCR_TRG 0x00000200
1033 #define SCR_ACK 0x00000040
1034 #define SCR_ATN 0x00000008
1057 #define SCR_NO_FLUSH 0x01000000
1059 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1060 #define SCR_COPY_F(n) (0xc0000000 | (n))
1069 ** << 0 >>
1072 ** << 0 >>
1075 ** << 0 >>
1081 ** offset 0x80. Bit 7 of register offset is stored in
1086 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1089 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1092 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1095 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1098 #define SCR_LOAD 0x00000000
1099 #define SCR_SHL 0x01000000
1100 #define SCR_OR 0x02000000
1101 #define SCR_XOR 0x03000000
1102 #define SCR_AND 0x04000000
1103 #define SCR_SHR 0x05000000
1104 #define SCR_ADD 0x06000000
1105 #define SCR_ADDC 0x07000000
1107 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1112 ** << 0 >>
1115 ** << 0 >>
1118 ** << 0 >>
1121 ** << 0 >>
1127 SCR_REG_SFBR(reg,SCR_OR,0)
1130 SCR_SFBR_REG(reg,SCR_OR,0)
1156 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1157 #define SCR_NO_FLUSH2 0x02000000
1158 #define SCR_DSA_REL2 0x10000000
1161 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1164 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1168 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1173 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1213 #define SCR_NO_OP 0x80000000
1214 #define SCR_JUMP 0x80080000
1215 #define SCR_JUMP64 0x80480000
1216 #define SCR_JUMPR 0x80880000
1217 #define SCR_CALL 0x88080000
1218 #define SCR_CALLR 0x88880000
1219 #define SCR_RETURN 0x90080000
1220 #define SCR_INT 0x98080000
1221 #define SCR_INT_FLY 0x98180000
1223 #define IFFALSE(arg) (0x00080000 | (arg))
1224 #define IFTRUE(arg) (0x00000000 | (arg))
1226 #define WHEN(phase) (0x00030000 | (phase))
1227 #define IF(phase) (0x00020000 | (phase))
1229 #define DATA(D) (0x00040000 | ((D) & 0xff))
1230 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1232 #define CARRYSET (0x00200000)
1255 } while (0)