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/linux-6.12.1/sound/soc/qcom/
Dlpass-ipq806x.c95 return 0; in ipq806x_lpass_exit()
108 return 0; in ipq806x_lpass_free_dma_channel()
112 .i2sctrl_reg_base = 0x0010,
113 .i2sctrl_reg_stride = 0x04,
115 .irq_reg_base = 0x3000,
116 .irq_reg_stride = 0x1000,
118 .rdma_reg_base = 0x6000,
119 .rdma_reg_stride = 0x1000,
121 .wrdma_reg_base = 0xB000,
122 .wrdma_reg_stride = 0x1000,
[all …]
Dlpass-apq8016.c127 int chan = 0; in apq8016_lpass_alloc_dma_channel()
154 return 0; in apq8016_lpass_free_dma_channel()
171 for (i = 0; i < drvdata->num_clks; i++) in apq8016_lpass_init()
208 return 0; in apq8016_lpass_init()
222 return 0; in apq8016_lpass_exit()
227 .i2sctrl_reg_base = 0x1000,
228 .i2sctrl_reg_stride = 0x1000,
230 .irq_reg_base = 0x6000,
231 .irq_reg_stride = 0x1000,
233 .rdma_reg_base = 0x8400,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/nvmem/
Dqcom,spmi-sdam.yaml42 #size-cells = <0>;
46 reg = <0xb000>;
49 ranges = <0 0xb000 0x100>;
53 reg = <0x50 0x1>;
/linux-6.12.1/drivers/clk/qcom/
Dturingcc-qcs404.c24 .halt_reg = 0x5098,
27 .enable_reg = 0x5098,
28 .enable_mask = BIT(0),
37 .halt_reg = 0x9000,
40 .enable_reg = 0x9000,
41 .enable_mask = BIT(0),
50 .halt_reg = 0xb000,
53 .enable_reg = 0xb000,
54 .enable_mask = BIT(0),
63 .halt_reg = 0x10000,
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/adreno/
Dadreno_gen7_2_0_snapshot.h99 {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
100 {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
101 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
102 {A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
103 {A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
104 {A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
105 {A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
106 {A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
107 {A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
108 {A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
[all …]
Dadreno_gen7_0_0_snapshot.h85 {A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
86 {A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
87 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
88 {A7XX_SP_INST_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
89 {A7XX_SP_INST_DATA_1, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
90 {A7XX_SP_LB_0_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
91 {A7XX_SP_LB_1_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
92 {A7XX_SP_LB_2_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
93 {A7XX_SP_LB_3_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
94 {A7XX_SP_LB_4_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
[all …]
Dadreno_gen7_9_0_snapshot.h121 { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
122 { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
123 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
124 { A7XX_SP_INST_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
125 { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
126 { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
127 { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
128 { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
129 { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
130 { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/
Dif_defs.h19 #define HIVE_IF_FRAME_REQUEST 0xA000
20 #define HIVE_IF_LINES_REQUEST 0xB000
21 #define HIVE_IF_VECTORS_REQUEST 0xC000
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dmediatek,mdp3-tcc.yaml59 reg = <0x1400b000 0x1000>;
60 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
/linux-6.12.1/drivers/leds/rgb/
Dleds-qcom-lpg.c19 #define LPG_SUBTYPE_REG 0x05
20 #define LPG_SUBTYPE_LPG 0x2
21 #define LPG_SUBTYPE_PWM 0xb
22 #define LPG_SUBTYPE_HI_RES_PWM 0xc
23 #define LPG_SUBTYPE_LPG_LITE 0x11
24 #define LPG_PATTERN_CONFIG_REG 0x40
25 #define LPG_SIZE_CLK_REG 0x41
26 #define PWM_CLK_SELECT_MASK GENMASK(1, 0)
27 #define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)
29 #define LPG_PREDIV_CLK_REG 0x42
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dpmk8350.dtsi13 #define PMK8350_SID 0
21 mode-recovery = <0x01>;
22 mode-bootloader = <0x02>;
31 #size-cells = <0>;
35 reg = <0x1300>, <0x800>;
40 interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
47 interrupts = <PMK8350_SID 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
54 reg = <0x3100>;
56 #size-cells = <0>;
57 interrupts = <PMK8350_SID 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6ulz-bsh-smm-m2.dts27 pinctrl-0 = <&pinctrl_gpmi_nand>;
38 pinctrl-0 = <&pinctrl_uart3>;
53 pinctrl-0 = <&pinctrl_uart4>;
71 #size-cells = <0>;
73 pinctrl-0 = <&pinctrl_wlan>;
99 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
100 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
101 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
102 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
103 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
[all …]
Dimx6q-arm2.dts17 reg = <0x10000000 0x80000000>;
33 gpio = <&gpio3 22 0>;
42 gpios = <&gpio3 25 0>;
50 pinctrl-0 = <&pinctrl_gpmi_nand>;
56 pinctrl-0 = <&pinctrl_hog>;
61 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
67 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
68 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
69 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
70 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
[all …]
/linux-6.12.1/arch/arm/boot/dts/arm/
Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/linux-6.12.1/drivers/media/platform/mediatek/vcodec/decoder/
Dvdec_ipi_msg.h16 AP_IPIMSG_DEC_INIT = 0xA000,
17 AP_IPIMSG_DEC_START = 0xA001,
18 AP_IPIMSG_DEC_END = 0xA002,
19 AP_IPIMSG_DEC_DEINIT = 0xA003,
20 AP_IPIMSG_DEC_RESET = 0xA004,
21 AP_IPIMSG_DEC_CORE = 0xA005,
22 AP_IPIMSG_DEC_CORE_END = 0xA006,
23 AP_IPIMSG_DEC_GET_PARAM = 0xA007,
25 VPU_IPIMSG_DEC_INIT_ACK = 0xB000,
26 VPU_IPIMSG_DEC_START_ACK = 0xB001,
[all …]
/linux-6.12.1/drivers/usb/serial/
Dpl2303.h6 #define BENQ_VENDOR_ID 0x04a5
7 #define BENQ_PRODUCT_ID_S81 0x4027
9 #define PL2303_VENDOR_ID 0x067b
10 #define PL2303_PRODUCT_ID 0x2303
11 #define PL2303_PRODUCT_ID_TB 0x2304
12 #define PL2303_PRODUCT_ID_GC 0x23a3
13 #define PL2303_PRODUCT_ID_GB 0x23b3
14 #define PL2303_PRODUCT_ID_GT 0x23c3
15 #define PL2303_PRODUCT_ID_GL 0x23d3
16 #define PL2303_PRODUCT_ID_GE 0x23e3
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Drv770_smc.h30 #define RV770_SMC_TABLE_ADDRESS 0xB000
113 #define SMC_STROBE_RATIO 0x0F
114 #define SMC_STROBE_ENABLE 0x10
116 #define SMC_MC_EDC_RD_FLAG 0x01
117 #define SMC_MC_EDC_WR_FLAG 0x02
118 #define SMC_MC_RTT_ENABLE 0x04
119 #define SMC_MC_STUTTER_EN 0x08
133 #define RV770_SMC_VOLTAGEMASK_VDDC 0
163 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
167 #define RV770_SMC_SOFT_REGISTERS_START 0x104
[all …]
/linux-6.12.1/drivers/usb/core/
Dquirks.c49 quirk_count = 0; in quirks_param_set()
55 for (quirk_count = 1, i = 0; val[i]; i++) in quirks_param_set()
67 quirk_count = 0; in quirks_param_set()
73 for (i = 0, p = val; p && *p;) { in quirks_param_set()
94 for (flags = 0; *field; field++) { in quirks_param_set()
159 return 0; in quirks_param_set()
194 { USB_DEVICE(0x0204, 0x6025), .driver_info = USB_QUIRK_RESET_RESUME },
197 { USB_DEVICE(0x0218, 0x0201), .driver_info =
201 { USB_DEVICE(0x0218, 0x0401), .driver_info =
205 { USB_DEVICE(0x03f0, 0x0701), .driver_info =
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/linux-6.12.1/drivers/input/misc/
Diqs7222.c25 #define IQS7222_PROD_NUM 0x00
31 #define IQS7222_SYS_STATUS 0x10
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
48 #define IQS7222_SYS_SETUP 0xD0
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
63 #define IQS7222_COMMS_HOLD BIT(0)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsamsung,exynos7-clock.yaml254 #clock-cells = <0>;
260 reg = <0x105e0000 0xb000>;
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,ethdr.yaml55 - description: video frontend 0 clock
57 - description: graphic frontend 0 clock
61 - description: video frontend 0 async clock
63 - description: graphic frontend 0 async clock
89 - description: video frontend 0 async reset
91 - description: graphic frontend 0 async reset
140 reg = <0 0x1c114000 0 0x1000>,
141 <0 0x1c115000 0 0x1000>,
142 <0 0x1c117000 0 0x1000>,
143 <0 0x1c119000 0 0x1000>,
[all …]
/linux-6.12.1/arch/loongarch/include/asm/
Dcpu.h18 * 31 24 23 16 15 12 11 0
25 #define PRID_COMP_MASK 0xff0000
27 #define PRID_COMP_LOONGSON 0x140000
35 #define PRID_SERIES_MASK 0xf000
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
44 * Particular Product ID values for bits 11:0 of the PRID register.
[all …]

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