Lines Matching +full:0 +full:xb000
17 reg = <0x10000000 0x80000000>;
33 gpio = <&gpio3 22 0>;
42 gpios = <&gpio3 25 0>;
50 pinctrl-0 = <&pinctrl_gpmi_nand>;
56 pinctrl-0 = <&pinctrl_hog>;
61 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
67 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
68 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
69 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
70 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
71 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
72 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
73 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
74 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
75 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
76 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
77 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
78 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
79 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
80 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
81 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
82 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
88 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
89 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
90 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
91 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
92 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
93 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
94 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
95 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
96 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
97 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
98 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
99 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
100 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
101 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
102 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
103 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
104 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
110 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
111 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
112 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
113 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
119 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
120 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
126 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
132 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
133 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
134 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
135 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
136 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
137 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
138 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
139 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
140 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
141 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
147 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
148 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
154 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
155 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
156 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
157 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
158 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
159 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
160 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
161 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
162 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
163 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
171 pinctrl-0 = <&pinctrl_enet>;
175 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
183 pinctrl-0 = <&pinctrl_usbotg>;
193 pinctrl-0 = <&pinctrl_usdhc3
202 pinctrl-0 = <&pinctrl_usdhc4>;
208 pinctrl-0 = <&pinctrl_uart2>;
216 pinctrl-0 = <&pinctrl_uart4>;