Lines Matching +full:0 +full:xb000
25 #define IQS7222_PROD_NUM 0x00
31 #define IQS7222_SYS_STATUS 0x10
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
48 #define IQS7222_SYS_SETUP 0xD0
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
63 #define IQS7222_COMMS_HOLD BIT(0)
64 #define IQS7222_COMMS_ERROR 0xEEEE
85 #define IQS7222_REG_OFFSET 0x100
165 .mask = BIT(0),
166 .val = BIT(0),
167 .enable = BIT(0),
207 .link = BIT(0),
208 .mask = BIT(0),
209 .val = BIT(0),
210 .enable = BIT(0),
324 .base = 0x8000,
329 .base = 0x8700,
334 .base = 0x9000,
339 .base = 0xA000,
344 .base = 0xAC00,
349 .base = 0xB000,
354 .base = 0xC000,
382 .base = 0x8000,
387 .base = 0x8700,
392 .base = 0x9000,
397 .base = 0xA000,
402 .base = 0xAC00,
407 .base = 0xB000,
412 .base = 0xC000,
436 .base = 0x8000,
441 .base = 0x8A00,
446 .base = 0x9000,
451 .base = 0xB000,
456 .base = 0xC400,
478 .base = 0x8000,
483 .base = 0x8A00,
488 .base = 0x9000,
493 .base = 0xB000,
498 .base = 0xC400,
525 .base = 0x8000,
530 .base = 0x8500,
535 .base = 0x9000,
540 .base = 0xA000,
545 .base = 0xAA00,
550 .base = 0xB000,
555 .base = 0xC000,
582 .base = 0x8000,
587 .base = 0x8500,
592 .base = 0x9000,
597 .base = 0xA000,
602 .base = 0xAA00,
607 .base = 0xB000,
612 .base = 0xC000,
638 .base = 0x8000,
643 .base = 0x8700,
648 .base = 0x9000,
653 .base = 0xA000,
658 .base = 0xAE00,
663 .base = 0xB000,
668 .base = 0xC000,
694 .base = 0x8000,
699 .base = 0x8700,
704 .base = 0x9000,
709 .base = 0xA000,
714 .base = 0xAE00,
719 .base = 0xB000,
724 .base = 0xC000,
737 .fw_major = 0,
750 .base = 0x8000,
755 .base = 0x8700,
760 .base = 0x9000,
765 .base = 0xA000,
770 .base = 0xAE00,
775 .base = 0xB000,
780 .base = 0xC000,
811 .reg_offset = 0,
819 .reg_offset = 0,
820 .reg_shift = 0,
857 .reg_shift = 0,
881 .reg_shift = 0,
888 .reg_offset = 0,
896 .reg_offset = 0,
913 .reg_shift = 0,
921 .reg_shift = 0,
928 .reg_offset = 0,
936 .reg_offset = 0,
943 .reg_offset = 0,
950 .reg_offset = 0,
957 .reg_offset = 0,
964 .reg_offset = 0,
971 .reg_offset = 0,
972 .reg_shift = 0,
998 .reg_shift = 0,
1023 .reg_shift = 0,
1039 .reg_shift = 0,
1047 .reg_offset = 0,
1056 .reg_offset = 0,
1065 .reg_offset = 0,
1066 .reg_shift = 0,
1076 .reg_shift = 0,
1092 .reg_offset = 0,
1100 .reg_offset = 0,
1108 .reg_offset = 0,
1116 .reg_offset = 0,
1117 .reg_shift = 0,
1133 .reg_shift = 0,
1140 .reg_offset = 0,
1149 .reg_offset = 0,
1157 .reg_offset = 0,
1166 .reg_offset = 0,
1174 .reg_offset = 0,
1191 .reg_shift = 0,
1260 .reg_shift = 0,
1270 .reg_shift = 0,
1278 .reg_offset = 0,
1288 .reg_offset = 0,
1289 .reg_shift = 0,
1307 .reg_shift = 0,
1323 .reg_shift = 0,
1340 .reg_shift = 0,
1369 .reg_shift = 0,
1379 .reg_shift = 0,
1388 .reg_shift = 0,
1395 .reg_offset = 0,
1403 .reg_shift = 0,
1412 .reg_shift = 0,
1420 .reg_shift = 0,
1428 .reg_shift = 0,
1437 .reg_shift = 0,
1445 .reg_shift = 0,
1454 .reg_shift = 0,
1462 .reg_shift = 0,
1537 if (ret < 0) in iqs7222_irq_poll()
1539 else if (ret > 0) in iqs7222_irq_poll()
1540 return 0; in iqs7222_irq_poll()
1541 } while (ktime_compare(ktime_get(), irq_timeout) < 0); in iqs7222_irq_poll()
1552 return 0; in iqs7222_hard_reset()
1557 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); in iqs7222_hard_reset()
1568 u8 msg_buf[] = { 0xFF, }; in iqs7222_force_comms()
1574 * ever all write data is ignored, and all read data returns 0xEE. in iqs7222_force_comms()
1585 if (ret < 0) in iqs7222_force_comms()
1587 else if (ret > 0) in iqs7222_force_comms()
1588 return 0; in iqs7222_force_comms()
1592 if (ret >= 0) in iqs7222_force_comms()
1615 .flags = 0, in iqs7222_read_burst()
1637 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_read_burst()
1639 if (ret < 0) in iqs7222_read_burst()
1644 if (ret >= 0) in iqs7222_read_burst()
1656 ret = 0; in iqs7222_read_burst()
1666 if (ret < 0) in iqs7222_read_burst()
1668 "Failed to read from address 0x%04X: %d\n", reg, ret); in iqs7222_read_burst()
1684 return 0; in iqs7222_read_word()
1717 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_write_burst()
1719 if (ret < 0) in iqs7222_write_burst()
1724 if (ret >= 0) in iqs7222_write_burst()
1731 ret = 0; in iqs7222_write_burst()
1739 if (ret < 0) in iqs7222_write_burst()
1741 "Failed to write to address 0x%04X: %d\n", reg, ret); in iqs7222_write_burst()
1757 u16 sys_status = 0; in iqs7222_ati_trigger()
1771 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_ati_trigger()
1796 return 0; in iqs7222_ati_trigger()
1815 } while (ktime_compare(ktime_get(), ati_timeout) < 0); in iqs7222_ati_trigger()
1818 "ATI attempt %d of %d failed with status 0x%02X, %s\n", in iqs7222_ati_trigger()
1847 iqs7222->sys_setup[0] | in iqs7222_dev_init()
1856 iqs7222->filt_setup[1] &= GENMASK(7, 0); in iqs7222_dev_init()
1857 iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0)); in iqs7222_dev_init()
1881 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { in iqs7222_dev_init()
1891 val = iqs7222_setup(iqs7222, i, 0); in iqs7222_dev_init()
1899 for (j = 0; j < num_row; j++) { in iqs7222_dev_init()
1904 for (k = 0; k < num_col; k++) in iqs7222_dev_init()
1909 for (k = 0; k < num_col; k++) in iqs7222_dev_init()
1949 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; in iqs7222_dev_init()
1950 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; in iqs7222_dev_init()
1951 return 0; in iqs7222_dev_init()
1969 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { in iqs7222_dev_info()
1970 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) in iqs7222_dev_info()
1982 return 0; in iqs7222_dev_info()
1990 le16_to_cpu(dev_id[0])); in iqs7222_dev_info()
2006 return 0; in iqs7222_gpio_select()
2009 return 0; in iqs7222_gpio_select()
2016 } else if (count < 0) { in iqs7222_gpio_select()
2031 for (i = 0; i < count; i++) { in iqs7222_gpio_select()
2049 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; in iqs7222_gpio_select()
2054 return 0; in iqs7222_gpio_select()
2068 return 0; in iqs7222_parse_props()
2070 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { in iqs7222_parse_props()
2122 val_max = GENMASK(reg_width - 1, 0) * val_pitch; in iqs7222_parse_props()
2135 return 0; in iqs7222_parse_props()
2162 return 0; in iqs7222_parse_event()
2171 return 0; in iqs7222_parse_event()
2190 return 0; in iqs7222_parse_event()
2211 return 0; in iqs7222_parse_cycle()
2214 if (count < 0) { in iqs7222_parse_cycle()
2234 for (i = 0; i < count; i++) { in iqs7222_parse_cycle()
2244 return 0; in iqs7222_parse_cycle()
2263 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; in iqs7222_parse_chan()
2295 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; in iqs7222_parse_chan()
2320 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; in iqs7222_parse_chan()
2333 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; in iqs7222_parse_chan()
2347 if (count < 0) { in iqs7222_parse_chan()
2369 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); in iqs7222_parse_chan()
2371 for (i = 0; i < count; i++) { in iqs7222_parse_chan()
2372 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; in iqs7222_parse_chan()
2381 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); in iqs7222_parse_chan()
2385 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { in iqs7222_parse_chan()
2429 dev_desc->touch_link - (i ? 0 : 2), in iqs7222_parse_chan()
2469 if (count < 0) { in iqs7222_parse_sldr()
2493 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; in iqs7222_parse_sldr()
2495 sldr_setup[0] |= count; in iqs7222_parse_sldr()
2496 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0); in iqs7222_parse_sldr()
2498 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { in iqs7222_parse_sldr()
2499 sldr_setup[5 + reg_offset + i] = 0; in iqs7222_parse_sldr()
2582 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); in iqs7222_parse_sldr()
2591 sldr_setup[0] &= ~dev_desc->wheel_enable; in iqs7222_parse_sldr()
2593 sldr_setup[0] |= dev_desc->wheel_enable; in iqs7222_parse_sldr()
2602 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) in iqs7222_parse_sldr()
2605 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { in iqs7222_parse_sldr()
2654 * coordinate field reports 0xFFFF and solely relies on touch in iqs7222_parse_sldr()
2695 if (count < 0) { in iqs7222_parse_tpad()
2714 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0); in iqs7222_parse_tpad()
2716 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { in iqs7222_parse_tpad()
2717 tpad_setup[8 + i] = 0; in iqs7222_parse_tpad()
2739 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) in iqs7222_parse_tpad()
2743 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) { in iqs7222_parse_tpad()
2772 * coordinate fields report 0xFFFF and solely relies on touch in iqs7222_parse_tpad()
2783 if (!iqs7222->tp_code[0]) in iqs7222_parse_tpad()
2784 return 0; in iqs7222_parse_tpad()
2787 0, (tpad_setup[4] ? : 1) - 1, 0, 0); in iqs7222_parse_tpad()
2790 0, (tpad_setup[5] ? : 1) - 1, 0, 0); in iqs7222_parse_tpad()
2803 return 0; in iqs7222_parse_tpad()
2837 return 0; in iqs7222_parse_reg_grp()
2864 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { in iqs7222_parse_all()
2867 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; in iqs7222_parse_all()
2868 gpio_setup[1] = 0; in iqs7222_parse_all()
2869 gpio_setup[2] = 0; in iqs7222_parse_all()
2878 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) in iqs7222_parse_all()
2879 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); in iqs7222_parse_all()
2881 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); in iqs7222_parse_all()
2884 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { in iqs7222_parse_all()
2887 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; in iqs7222_parse_all()
2888 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; in iqs7222_parse_all()
2890 chan_setup[5] = 0; in iqs7222_parse_all()
2893 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { in iqs7222_parse_all()
2896 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; in iqs7222_parse_all()
2899 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { in iqs7222_parse_all()
2900 for (j = 0; j < reg_grps[i].num_row; j++) { in iqs7222_parse_all()
2907 return 0; in iqs7222_parse_all()
2924 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { in iqs7222_report()
2929 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { in iqs7222_report()
2934 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) in iqs7222_report()
2935 return 0; in iqs7222_report()
2937 for (i = 0; i < num_chan; i++) { in iqs7222_report()
2940 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) in iqs7222_report()
2943 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { in iqs7222_report()
2964 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { in iqs7222_report()
2969 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) in iqs7222_report()
2976 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0], in iqs7222_report()
3006 iqs7222->sl_code[i][j], 0); in iqs7222_report()
3009 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) { in iqs7222_report()
3014 input_report_key(iqs7222->keypad, iqs7222->tp_code[0], in iqs7222_report()
3041 iqs7222->tp_code[j], 0); in iqs7222_report()
3046 return 0; in iqs7222_report()
3129 if (irq < 0) in iqs7222_probe()