Home
last modified time | relevance | path

Searched +full:0 +full:xb (Results 1 – 25 of 1054) sorted by relevance

12345678910>>...43

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/thm/
Dthm_13_0_2_sh_mask.h30 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
31 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
32 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
33 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
34 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
35 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
36 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
37 …N_CUR_TMP__MCM_EN__SHIFT 0x14
38 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
39 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
Dthm_9_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
Dthm_10_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux-6.12.1/drivers/pinctrl/nuvoton/
Dpinctrl-ma35d1.c21 MA35_PIN(0, PA0, 0x80, 0x0,
22 MA35_MUX(0x0, "GPA0"),
23 MA35_MUX(0x2, "UART1_nCTS"),
24 MA35_MUX(0x3, "UART16_RXD"),
25 MA35_MUX(0x6, "NAND_DATA0"),
26 MA35_MUX(0x7, "EBI_AD0"),
27 MA35_MUX(0x9, "EBI_ADR0")),
28 MA35_PIN(1, PA1, 0x80, 0x4,
29 MA35_MUX(0x0, "GPA1"),
30 MA35_MUX(0x2, "UART1_nRTS"),
[all …]
/linux-6.12.1/drivers/ata/pata_parport/
Dktti.c20 #define j44(a, b) (((a >> 4) & 0x0f) | (b & 0xf0))
23 * cont = 0 - access the IDE register file
26 static int cont_map[2] = { 0x10, 0x08 };
32 w0(r); w2(0xb); w2(0xa); w2(3); w2(6); in ktti_write_regr()
33 w0(val); w2(3); w0(0); w2(6); w2(0xb); in ktti_write_regr()
42 w0(r); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_regr()
43 a = r1(); w2(0xc); b = r1(); w2(9); w2(0xc); w2(9); in ktti_read_regr()
51 for (k = 0; k < count / 2; k++) { in ktti_read_block()
52 w0(0x10); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_block()
53 a = r1(); w2(0xc); b = r1(); w2(9); in ktti_read_block()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/linux-6.12.1/drivers/pinctrl/mvebu/
Dpinctrl-kirkwood.c20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
35 MPP_MODE(0,
36 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
[all …]
/linux-6.12.1/arch/powerpc/math-emu/
Dmath_efp.c32 #define EFAPU 0x4
34 #define VCT 0x4
35 #define SPFP 0x6
36 #define DPFP 0x7
38 #define EFSADD 0x2c0
39 #define EFSSUB 0x2c1
40 #define EFSABS 0x2c4
41 #define EFSNABS 0x2c5
42 #define EFSNEG 0x2c6
43 #define EFSMUL 0x2c8
[all …]
Dmath.c29 void *op4) { return 0; }
80 #define OP31 0x1f /* 31 */
81 #define LFS 0x30 /* 48 */
82 #define LFSU 0x31 /* 49 */
83 #define LFD 0x32 /* 50 */
84 #define LFDU 0x33 /* 51 */
85 #define STFS 0x34 /* 52 */
86 #define STFSU 0x35 /* 53 */
87 #define STFD 0x36 /* 54 */
88 #define STFDU 0x37 /* 55 */
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
Ddpcs_3_1_4_sh_mask.h33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1
35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3
37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7
39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9
41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa
42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb
[all …]
Ddpcs_4_2_2_sh_mask.h14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
Ddpcs_4_2_0_sh_mask.h27 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
28 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
30 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
31 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
36 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
37 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
39 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
40 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
45 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
46 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux-6.12.1/drivers/char/xillybus/
Dxillyusb.c55 #define USB_VENDOR_ID_XILINX 0x03fd
56 #define USB_VENDOR_ID_ALTERA 0x09fb
58 #define USB_PRODUCT_ID_XILLYUSB 0xebbe
198 OPCODE_DATA = 0,
207 OPCODE_QUIESCE = 0,
228 unsigned int done = 0; in fifo_write()
242 if (n == 0) { in fifo_write()
268 writepos = 0; in fifo_write()
272 writebuf = 0; in fifo_write()
281 unsigned int done = 0; in fifo_read()
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-104-dio-48e.c32 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
37 module_param_hw_array(irq, uint, irq, &num_irq, 0);
40 #define DIO48E_ENABLE_INTERRUPT 0xB
42 #define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD
44 #define DIO48E_CLEAR_INTERRUPT 0xF
49 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB),
50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF),
53 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6),
54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
55 regmap_reg_range(0xF, 0xF),
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_5_0_0_sh_mask.h29 …P_CTRL__STANDARD__SHIFT 0x0
30 …P_CTRL__STD_VERSION__SHIFT 0x4
31 …STANDARD_MASK 0x0000000FL
32 …STD_VERSION_MASK 0x00000010L
34 …C_GATE__SYS__SHIFT 0x0
35 …C_GATE__UDEC__SHIFT 0x1
36 …C_GATE__MPEG2__SHIFT 0x2
37 …C_GATE__REGS__SHIFT 0x3
38 …C_GATE__RBC__SHIFT 0x4
39 …C_GATE__LMI_MC__SHIFT 0x5
[all …]
Dvcn_4_0_5_sh_mask.h30 …C_GATE__SYS__SHIFT 0x0
31 …C_GATE__UDEC__SHIFT 0x1
32 …C_GATE__MPEG2__SHIFT 0x2
33 …C_GATE__REGS__SHIFT 0x3
34 …C_GATE__RBC__SHIFT 0x4
35 …C_GATE__LMI_MC__SHIFT 0x5
36 …C_GATE__LMI_UMC__SHIFT 0x6
37 …C_GATE__IDCT__SHIFT 0x7
38 …C_GATE__MPRD__SHIFT 0x8
39 …C_GATE__MPC__SHIFT 0x9
[all …]
/linux-6.12.1/drivers/phy/starfive/
Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h28 DC_IH_SRC_ID_START = 0x1,
29 DC_IH_SRC_ID_END = 0x1f,
30 VGA_IH_SRC_ID_START = 0x20,
31 VGA_IH_SRC_ID_END = 0x27,
32 CAP_IH_SRC_ID_START = 0x28,
33 CAP_IH_SRC_ID_END = 0x2f,
34 VIP_IH_SRC_ID_START = 0x30,
35 VIP_IH_SRC_ID_END = 0x3f,
36 ROM_IH_SRC_ID_START = 0x40,
37 ROM_IH_SRC_ID_END = 0x5d,
[all …]

12345678910>>...43