1 /* 2 * OSS_2_4 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef OSS_2_4_ENUM_H 25 #define OSS_2_4_ENUM_H 26 27 typedef enum IH_CLIENT_ID { 28 DC_IH_SRC_ID_START = 0x1, 29 DC_IH_SRC_ID_END = 0x1f, 30 VGA_IH_SRC_ID_START = 0x20, 31 VGA_IH_SRC_ID_END = 0x27, 32 CAP_IH_SRC_ID_START = 0x28, 33 CAP_IH_SRC_ID_END = 0x2f, 34 VIP_IH_SRC_ID_START = 0x30, 35 VIP_IH_SRC_ID_END = 0x3f, 36 ROM_IH_SRC_ID_START = 0x40, 37 ROM_IH_SRC_ID_END = 0x5d, 38 BIF_IH_SRC_ID_START = 0x5e, 39 SAM_IH_SRC_ID_START = 0x5f, 40 SRBM_IH_SRC_ID_START = 0x60, 41 SRBM_IH_SRC_ID_END = 0x67, 42 UVD_IH_SRC_ID_START = 0x72, 43 UVD_IH_SRC_ID_END = 0x85, 44 VMC_IH_SRC_ID_START = 0x86, 45 VMC_IH_SRC_ID_END = 0x8f, 46 RLC_IH_SRC_ID_START = 0x90, 47 RLC_IH_SRC_ID_END = 0xf3, 48 PDMA_IH_SRC_ID_START = 0xf4, 49 PDMA_IH_SRC_ID_END = 0xf7, 50 CG_IH_SRC_ID_START = 0xf8, 51 CG_IH_SRC_ID_END = 0xff, 52 } IH_CLIENT_ID; 53 typedef enum IH_PERF_SEL { 54 IH_PERF_SEL_CYCLE = 0x0, 55 IH_PERF_SEL_IDLE = 0x1, 56 IH_PERF_SEL_INPUT_IDLE = 0x2, 57 IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, 58 IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, 59 IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, 60 IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, 61 IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, 62 IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, 63 IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, 64 IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, 65 IH_PERF_SEL_RB_IDLE = 0xb, 66 IH_PERF_SEL_RB_FULL = 0xc, 67 IH_PERF_SEL_RB_OVERFLOW = 0xd, 68 IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, 69 IH_PERF_SEL_RB_WPTR_WRAP = 0xf, 70 IH_PERF_SEL_RB_RPTR_WRAP = 0x10, 71 IH_PERF_SEL_MC_WR_IDLE = 0x11, 72 IH_PERF_SEL_MC_WR_COUNT = 0x12, 73 IH_PERF_SEL_MC_WR_STALL = 0x13, 74 IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, 75 IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, 76 IH_PERF_SEL_BIF_RISING = 0x16, 77 IH_PERF_SEL_BIF_FALLING = 0x17, 78 IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, 79 IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, 80 IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, 81 IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, 82 IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, 83 IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, 84 IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, 85 IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, 86 IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, 87 IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, 88 IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, 89 IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, 90 IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, 91 IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, 92 } IH_PERF_SEL; 93 typedef enum SRBM_PERFCOUNT1_SEL { 94 SRBM_PERF_SEL_COUNT = 0x0, 95 SRBM_PERF_SEL_BIF_BUSY = 0x1, 96 SRBM_PERF_SEL_SDMA0_BUSY = 0x3, 97 SRBM_PERF_SEL_IH_BUSY = 0x4, 98 SRBM_PERF_SEL_MCB_BUSY = 0x5, 99 SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, 100 SRBM_PERF_SEL_MCC_BUSY = 0x7, 101 SRBM_PERF_SEL_MCD_BUSY = 0x8, 102 SRBM_PERF_SEL_CHUB_BUSY = 0x9, 103 SRBM_PERF_SEL_SEM_BUSY = 0xa, 104 SRBM_PERF_SEL_UVD_BUSY = 0xb, 105 SRBM_PERF_SEL_VMC_BUSY = 0xc, 106 SRBM_PERF_SEL_XSP_BUSY = 0xd, 107 SRBM_PERF_SEL_SDMA1_BUSY = 0xe, 108 SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, 109 SRBM_PERF_SEL_VCE0_BUSY = 0x10, 110 SRBM_PERF_SEL_XDMA_BUSY = 0x11, 111 SRBM_PERF_SEL_ACP_BUSY = 0x12, 112 SRBM_PERF_SEL_SDMA2_BUSY = 0x13, 113 SRBM_PERF_SEL_SDMA3_BUSY = 0x14, 114 SRBM_PERF_SEL_SAMSCP_BUSY = 0x15, 115 SRBM_PERF_SEL_VMC1_BUSY = 0x16, 116 SRBM_PERF_SEL_ISP_BUSY = 0x17, 117 SRBM_PERF_SEL_VCE1_BUSY = 0x18, 118 SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, 119 SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, 120 } SRBM_PERFCOUNT1_SEL; 121 typedef enum SYS_GRBM_GFX_INDEX_SEL { 122 GRBM_GFX_INDEX_BIF = 0x0, 123 GRBM_GFX_INDEX_SDMA0 = 0x1, 124 GRBM_GFX_INDEX_SDMA1 = 0x2, 125 RESEVERED0 = 0x3, 126 GRBM_GFX_INDEX_UVD = 0x4, 127 GRBM_GFX_INDEX_VCE0 = 0x5, 128 GRBM_GFX_INDEX_VCE1 = 0x6, 129 GRBM_GFX_INDEX_ACP = 0x7, 130 GRBM_GFX_INDEX_SMU = 0x8, 131 GRBM_GFX_INDEX_SAMMSP = 0x9, 132 GRBM_GFX_INDEX_SAMSCP = 0xa, 133 GRBM_GFX_INDEX_ISP = 0xb, 134 GRBM_GFX_INDEX_TST = 0xc, 135 GRBM_GFX_INDEX_SDMA2 = 0xd, 136 GRBM_GFX_INDEX_SDMA3 = 0xe, 137 } SYS_GRBM_GFX_INDEX_SEL; 138 typedef enum SRBM_GFX_CNTL_SEL { 139 SRBM_GFX_CNTL_BIF = 0x0, 140 SRBM_GFX_CNTL_SDMA0 = 0x1, 141 SRBM_GFX_CNTL_SDMA1 = 0x2, 142 SRBM_GFX_CNTL_GRBM = 0x3, 143 SRBM_GFX_CNTL_UVD = 0x4, 144 SRBM_GFX_CNTL_VCE0 = 0x5, 145 SRBM_GFX_CNTL_VCE1 = 0x6, 146 SRBM_GFX_CNTL_ACP = 0x7, 147 SRBM_GFX_CNTL_SMU = 0x8, 148 SRBM_GFX_CNTL_SAMMSP = 0x9, 149 SRBM_GFX_CNTL_SAMSCP = 0xa, 150 SRBM_GFX_CNTL_ISP = 0xb, 151 SRBM_GFX_CNTL_TST = 0xc, 152 SRBM_GFX_CNTL_SDMA2 = 0xd, 153 SRBM_GFX_CNTL_SDMA3 = 0xe, 154 } SRBM_GFX_CNTL_SEL; 155 typedef enum SDMA_PERF_SEL { 156 SDMA_PERF_SEL_CYCLE = 0x0, 157 SDMA_PERF_SEL_IDLE = 0x1, 158 SDMA_PERF_SEL_REG_IDLE = 0x2, 159 SDMA_PERF_SEL_RB_EMPTY = 0x3, 160 SDMA_PERF_SEL_RB_FULL = 0x4, 161 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, 162 SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, 163 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, 164 SDMA_PERF_SEL_RB_RPTR_WB = 0x8, 165 SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, 166 SDMA_PERF_SEL_RB_CMD_FULL = 0xa, 167 SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, 168 SDMA_PERF_SEL_IB_CMD_FULL = 0xc, 169 SDMA_PERF_SEL_EX_IDLE = 0xd, 170 SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, 171 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, 172 SDMA_PERF_SEL_MC_WR_IDLE = 0x10, 173 SDMA_PERF_SEL_MC_WR_COUNT = 0x11, 174 SDMA_PERF_SEL_MC_RD_IDLE = 0x12, 175 SDMA_PERF_SEL_MC_RD_COUNT = 0x13, 176 SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, 177 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, 178 SDMA_PERF_SEL_SEM_IDLE = 0x18, 179 SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, 180 SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, 181 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, 182 SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, 183 SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, 184 SDMA_PERF_SEL_INT_IDLE = 0x1e, 185 SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, 186 SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, 187 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, 188 SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, 189 SDMA_PERF_SEL_NUM_PACKET = 0x23, 190 SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, 191 SDMA_PERF_SEL_CE_WR_IDLE = 0x26, 192 SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, 193 SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, 194 SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, 195 SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, 196 SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, 197 SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, 198 SDMA_PERF_SEL_CE_INFO_FULL = 0x31, 199 SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, 200 SDMA_PERF_SEL_CE_RD_STALL = 0x33, 201 SDMA_PERF_SEL_CE_WR_STALL = 0x34, 202 SDMA_PERF_SEL_GFX_SELECT = 0x35, 203 SDMA_PERF_SEL_RLC0_SELECT = 0x36, 204 SDMA_PERF_SEL_RLC1_SELECT = 0x37, 205 SDMA_PERF_SEL_CTX_CHANGE = 0x38, 206 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, 207 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, 208 SDMA_PERF_SEL_DOORBELL = 0x3b, 209 SDMA_PERF_SEL_RD_BA_RTR = 0x3c, 210 SDMA_PERF_SEL_WR_BA_RTR = 0x3d, 211 } SDMA_PERF_SEL; 212 typedef enum SurfaceEndian { 213 ENDIAN_NONE = 0x0, 214 ENDIAN_8IN16 = 0x1, 215 ENDIAN_8IN32 = 0x2, 216 ENDIAN_8IN64 = 0x3, 217 } SurfaceEndian; 218 typedef enum ArrayMode { 219 ARRAY_LINEAR_GENERAL = 0x0, 220 ARRAY_LINEAR_ALIGNED = 0x1, 221 ARRAY_1D_TILED_THIN1 = 0x2, 222 ARRAY_1D_TILED_THICK = 0x3, 223 ARRAY_2D_TILED_THIN1 = 0x4, 224 ARRAY_PRT_TILED_THIN1 = 0x5, 225 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 226 ARRAY_2D_TILED_THICK = 0x7, 227 ARRAY_2D_TILED_XTHICK = 0x8, 228 ARRAY_PRT_TILED_THICK = 0x9, 229 ARRAY_PRT_2D_TILED_THICK = 0xa, 230 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 231 ARRAY_3D_TILED_THIN1 = 0xc, 232 ARRAY_3D_TILED_THICK = 0xd, 233 ARRAY_3D_TILED_XTHICK = 0xe, 234 ARRAY_PRT_3D_TILED_THICK = 0xf, 235 } ArrayMode; 236 typedef enum PipeTiling { 237 CONFIG_1_PIPE = 0x0, 238 CONFIG_2_PIPE = 0x1, 239 CONFIG_4_PIPE = 0x2, 240 CONFIG_8_PIPE = 0x3, 241 } PipeTiling; 242 typedef enum BankTiling { 243 CONFIG_4_BANK = 0x0, 244 CONFIG_8_BANK = 0x1, 245 } BankTiling; 246 typedef enum GroupInterleave { 247 CONFIG_256B_GROUP = 0x0, 248 CONFIG_512B_GROUP = 0x1, 249 } GroupInterleave; 250 typedef enum RowTiling { 251 CONFIG_1KB_ROW = 0x0, 252 CONFIG_2KB_ROW = 0x1, 253 CONFIG_4KB_ROW = 0x2, 254 CONFIG_8KB_ROW = 0x3, 255 CONFIG_1KB_ROW_OPT = 0x4, 256 CONFIG_2KB_ROW_OPT = 0x5, 257 CONFIG_4KB_ROW_OPT = 0x6, 258 CONFIG_8KB_ROW_OPT = 0x7, 259 } RowTiling; 260 typedef enum BankSwapBytes { 261 CONFIG_128B_SWAPS = 0x0, 262 CONFIG_256B_SWAPS = 0x1, 263 CONFIG_512B_SWAPS = 0x2, 264 CONFIG_1KB_SWAPS = 0x3, 265 } BankSwapBytes; 266 typedef enum SampleSplitBytes { 267 CONFIG_1KB_SPLIT = 0x0, 268 CONFIG_2KB_SPLIT = 0x1, 269 CONFIG_4KB_SPLIT = 0x2, 270 CONFIG_8KB_SPLIT = 0x3, 271 } SampleSplitBytes; 272 typedef enum NumPipes { 273 ADDR_CONFIG_1_PIPE = 0x0, 274 ADDR_CONFIG_2_PIPE = 0x1, 275 ADDR_CONFIG_4_PIPE = 0x2, 276 ADDR_CONFIG_8_PIPE = 0x3, 277 } NumPipes; 278 typedef enum PipeInterleaveSize { 279 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 280 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 281 } PipeInterleaveSize; 282 typedef enum BankInterleaveSize { 283 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 284 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 285 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 286 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 287 } BankInterleaveSize; 288 typedef enum NumShaderEngines { 289 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 290 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 291 } NumShaderEngines; 292 typedef enum ShaderEngineTileSize { 293 ADDR_CONFIG_SE_TILE_16 = 0x0, 294 ADDR_CONFIG_SE_TILE_32 = 0x1, 295 } ShaderEngineTileSize; 296 typedef enum NumGPUs { 297 ADDR_CONFIG_1_GPU = 0x0, 298 ADDR_CONFIG_2_GPU = 0x1, 299 ADDR_CONFIG_4_GPU = 0x2, 300 } NumGPUs; 301 typedef enum MultiGPUTileSize { 302 ADDR_CONFIG_GPU_TILE_16 = 0x0, 303 ADDR_CONFIG_GPU_TILE_32 = 0x1, 304 ADDR_CONFIG_GPU_TILE_64 = 0x2, 305 ADDR_CONFIG_GPU_TILE_128 = 0x3, 306 } MultiGPUTileSize; 307 typedef enum RowSize { 308 ADDR_CONFIG_1KB_ROW = 0x0, 309 ADDR_CONFIG_2KB_ROW = 0x1, 310 ADDR_CONFIG_4KB_ROW = 0x2, 311 } RowSize; 312 typedef enum NumLowerPipes { 313 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 314 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 315 } NumLowerPipes; 316 typedef enum DebugBlockId { 317 DBG_CLIENT_BLKID_RESERVED = 0x0, 318 DBG_CLIENT_BLKID_dbg = 0x1, 319 DBG_CLIENT_BLKID_uvdu_0 = 0x2, 320 DBG_CLIENT_BLKID_uvdu_1 = 0x3, 321 DBG_CLIENT_BLKID_uvdu_2 = 0x4, 322 DBG_CLIENT_BLKID_uvdu_3 = 0x5, 323 DBG_CLIENT_BLKID_uvdu_4 = 0x6, 324 DBG_CLIENT_BLKID_uvdu_5 = 0x7, 325 DBG_CLIENT_BLKID_uvdu_6 = 0x8, 326 DBG_CLIENT_BLKID_uvdb_0 = 0x9, 327 DBG_CLIENT_BLKID_uvdc_0 = 0xa, 328 DBG_CLIENT_BLKID_uvdc_1 = 0xb, 329 DBG_CLIENT_BLKID_uvdf_0 = 0xc, 330 DBG_CLIENT_BLKID_uvdf_1 = 0xd, 331 DBG_CLIENT_BLKID_uvdm_0 = 0xe, 332 DBG_CLIENT_BLKID_uvdm_1 = 0xf, 333 DBG_CLIENT_BLKID_uvdm_2 = 0x10, 334 DBG_CLIENT_BLKID_uvdm_3 = 0x11, 335 DBG_CLIENT_BLKID_vcea_0 = 0x12, 336 DBG_CLIENT_BLKID_vcea_1 = 0x13, 337 DBG_CLIENT_BLKID_vcea_2 = 0x14, 338 DBG_CLIENT_BLKID_vcea_3 = 0x15, 339 DBG_CLIENT_BLKID_vceb_0 = 0x16, 340 DBG_CLIENT_BLKID_vcec_0 = 0x17, 341 DBG_CLIENT_BLKID_dco = 0x18, 342 DBG_CLIENT_BLKID_xdma = 0x19, 343 DBG_CLIENT_BLKID_dci_pg = 0x1a, 344 DBG_CLIENT_BLKID_smu_0 = 0x1b, 345 DBG_CLIENT_BLKID_smu_1 = 0x1c, 346 DBG_CLIENT_BLKID_smu_2 = 0x1d, 347 DBG_CLIENT_BLKID_gck = 0x1e, 348 DBG_CLIENT_BLKID_tmonw0 = 0x1f, 349 DBG_CLIENT_BLKID_tmonw1 = 0x20, 350 DBG_CLIENT_BLKID_grbm = 0x21, 351 DBG_CLIENT_BLKID_rlc = 0x22, 352 DBG_CLIENT_BLKID_ds0 = 0x23, 353 DBG_CLIENT_BLKID_cpg_0 = 0x24, 354 DBG_CLIENT_BLKID_cpg_1 = 0x25, 355 DBG_CLIENT_BLKID_cpc_0 = 0x26, 356 DBG_CLIENT_BLKID_cpc_1 = 0x27, 357 DBG_CLIENT_BLKID_cpf_0 = 0x28, 358 DBG_CLIENT_BLKID_cpf_1 = 0x29, 359 DBG_CLIENT_BLKID_scf0 = 0x2a, 360 DBG_CLIENT_BLKID_scf1 = 0x2b, 361 DBG_CLIENT_BLKID_scf2 = 0x2c, 362 DBG_CLIENT_BLKID_scf3 = 0x2d, 363 DBG_CLIENT_BLKID_pc0 = 0x2e, 364 DBG_CLIENT_BLKID_pc1 = 0x2f, 365 DBG_CLIENT_BLKID_pc2 = 0x30, 366 DBG_CLIENT_BLKID_pc3 = 0x31, 367 DBG_CLIENT_BLKID_vgt0 = 0x32, 368 DBG_CLIENT_BLKID_vgt1 = 0x33, 369 DBG_CLIENT_BLKID_vgt2 = 0x34, 370 DBG_CLIENT_BLKID_vgt3 = 0x35, 371 DBG_CLIENT_BLKID_sx00 = 0x36, 372 DBG_CLIENT_BLKID_sx10 = 0x37, 373 DBG_CLIENT_BLKID_sx20 = 0x38, 374 DBG_CLIENT_BLKID_sx30 = 0x39, 375 DBG_CLIENT_BLKID_cb001 = 0x3a, 376 DBG_CLIENT_BLKID_cb200 = 0x3b, 377 DBG_CLIENT_BLKID_cb201 = 0x3c, 378 DBG_CLIENT_BLKID_cbr0 = 0x3d, 379 DBG_CLIENT_BLKID_cb000 = 0x3e, 380 DBG_CLIENT_BLKID_cb101 = 0x3f, 381 DBG_CLIENT_BLKID_cb300 = 0x40, 382 DBG_CLIENT_BLKID_cb301 = 0x41, 383 DBG_CLIENT_BLKID_cbr1 = 0x42, 384 DBG_CLIENT_BLKID_cb100 = 0x43, 385 DBG_CLIENT_BLKID_ia0 = 0x44, 386 DBG_CLIENT_BLKID_ia1 = 0x45, 387 DBG_CLIENT_BLKID_bci0 = 0x46, 388 DBG_CLIENT_BLKID_bci1 = 0x47, 389 DBG_CLIENT_BLKID_bci2 = 0x48, 390 DBG_CLIENT_BLKID_bci3 = 0x49, 391 DBG_CLIENT_BLKID_pa0 = 0x4a, 392 DBG_CLIENT_BLKID_pa1 = 0x4b, 393 DBG_CLIENT_BLKID_spim0 = 0x4c, 394 DBG_CLIENT_BLKID_spim1 = 0x4d, 395 DBG_CLIENT_BLKID_spim2 = 0x4e, 396 DBG_CLIENT_BLKID_spim3 = 0x4f, 397 DBG_CLIENT_BLKID_sdma = 0x50, 398 DBG_CLIENT_BLKID_ih = 0x51, 399 DBG_CLIENT_BLKID_sem = 0x52, 400 DBG_CLIENT_BLKID_srbm = 0x53, 401 DBG_CLIENT_BLKID_hdp = 0x54, 402 DBG_CLIENT_BLKID_acp_0 = 0x55, 403 DBG_CLIENT_BLKID_acp_1 = 0x56, 404 DBG_CLIENT_BLKID_sam = 0x57, 405 DBG_CLIENT_BLKID_mcc0 = 0x58, 406 DBG_CLIENT_BLKID_mcc1 = 0x59, 407 DBG_CLIENT_BLKID_mcc2 = 0x5a, 408 DBG_CLIENT_BLKID_mcc3 = 0x5b, 409 DBG_CLIENT_BLKID_mcd0 = 0x5c, 410 DBG_CLIENT_BLKID_mcd1 = 0x5d, 411 DBG_CLIENT_BLKID_mcd2 = 0x5e, 412 DBG_CLIENT_BLKID_mcd3 = 0x5f, 413 DBG_CLIENT_BLKID_mcb = 0x60, 414 DBG_CLIENT_BLKID_vmc = 0x61, 415 DBG_CLIENT_BLKID_gmcon = 0x62, 416 DBG_CLIENT_BLKID_gdc_0 = 0x63, 417 DBG_CLIENT_BLKID_gdc_1 = 0x64, 418 DBG_CLIENT_BLKID_gdc_2 = 0x65, 419 DBG_CLIENT_BLKID_gdc_3 = 0x66, 420 DBG_CLIENT_BLKID_gdc_4 = 0x67, 421 DBG_CLIENT_BLKID_gdc_5 = 0x68, 422 DBG_CLIENT_BLKID_gdc_6 = 0x69, 423 DBG_CLIENT_BLKID_gdc_7 = 0x6a, 424 DBG_CLIENT_BLKID_gdc_8 = 0x6b, 425 DBG_CLIENT_BLKID_gdc_9 = 0x6c, 426 DBG_CLIENT_BLKID_gdc_10 = 0x6d, 427 DBG_CLIENT_BLKID_gdc_11 = 0x6e, 428 DBG_CLIENT_BLKID_gdc_12 = 0x6f, 429 DBG_CLIENT_BLKID_gdc_13 = 0x70, 430 DBG_CLIENT_BLKID_gdc_14 = 0x71, 431 DBG_CLIENT_BLKID_gdc_15 = 0x72, 432 DBG_CLIENT_BLKID_gdc_16 = 0x73, 433 DBG_CLIENT_BLKID_gdc_17 = 0x74, 434 DBG_CLIENT_BLKID_gdc_18 = 0x75, 435 DBG_CLIENT_BLKID_gdc_19 = 0x76, 436 DBG_CLIENT_BLKID_gdc_20 = 0x77, 437 DBG_CLIENT_BLKID_gdc_21 = 0x78, 438 DBG_CLIENT_BLKID_gdc_22 = 0x79, 439 DBG_CLIENT_BLKID_gdc_23 = 0x7a, 440 DBG_CLIENT_BLKID_gdc_24 = 0x7b, 441 DBG_CLIENT_BLKID_gdc_25 = 0x7c, 442 DBG_CLIENT_BLKID_gdc_26 = 0x7d, 443 DBG_CLIENT_BLKID_gdc_27 = 0x7e, 444 DBG_CLIENT_BLKID_gdc_28 = 0x7f, 445 DBG_CLIENT_BLKID_wd = 0x80, 446 DBG_CLIENT_BLKID_sdma_0 = 0x81, 447 DBG_CLIENT_BLKID_sdma_1 = 0x82, 448 DBG_CLIENT_BLKID_sammsp = 0x83, 449 DBG_CLIENT_BLKID_dci_0 = 0x84, 450 DBG_CLIENT_BLKID_dccg0_0 = 0x85, 451 DBG_CLIENT_BLKID_dcfe01_0 = 0x86, 452 DBG_CLIENT_BLKID_dcfe02_0 = 0x87, 453 DBG_CLIENT_BLKID_dcfe03_0 = 0x88, 454 DBG_CLIENT_BLKID_dccg0_1 = 0x89, 455 } DebugBlockId; 456 typedef enum DebugBlockId_OLD { 457 DBG_BLOCK_ID_RESERVED = 0x0, 458 DBG_BLOCK_ID_DBG = 0x1, 459 DBG_BLOCK_ID_VMC = 0x2, 460 DBG_BLOCK_ID_PDMA = 0x3, 461 DBG_BLOCK_ID_CG = 0x4, 462 DBG_BLOCK_ID_SRBM = 0x5, 463 DBG_BLOCK_ID_GRBM = 0x6, 464 DBG_BLOCK_ID_RLC = 0x7, 465 DBG_BLOCK_ID_CSC = 0x8, 466 DBG_BLOCK_ID_SEM = 0x9, 467 DBG_BLOCK_ID_IH = 0xa, 468 DBG_BLOCK_ID_SC = 0xb, 469 DBG_BLOCK_ID_SQ = 0xc, 470 DBG_BLOCK_ID_AVP = 0xd, 471 DBG_BLOCK_ID_GMCON = 0xe, 472 DBG_BLOCK_ID_SMU = 0xf, 473 DBG_BLOCK_ID_DMA0 = 0x10, 474 DBG_BLOCK_ID_DMA1 = 0x11, 475 DBG_BLOCK_ID_SPIM = 0x12, 476 DBG_BLOCK_ID_GDS = 0x13, 477 DBG_BLOCK_ID_SPIS = 0x14, 478 DBG_BLOCK_ID_UNUSED0 = 0x15, 479 DBG_BLOCK_ID_PA0 = 0x16, 480 DBG_BLOCK_ID_PA1 = 0x17, 481 DBG_BLOCK_ID_CP0 = 0x18, 482 DBG_BLOCK_ID_CP1 = 0x19, 483 DBG_BLOCK_ID_CP2 = 0x1a, 484 DBG_BLOCK_ID_UNUSED1 = 0x1b, 485 DBG_BLOCK_ID_UVDU = 0x1c, 486 DBG_BLOCK_ID_UVDM = 0x1d, 487 DBG_BLOCK_ID_VCE = 0x1e, 488 DBG_BLOCK_ID_UNUSED2 = 0x1f, 489 DBG_BLOCK_ID_VGT0 = 0x20, 490 DBG_BLOCK_ID_VGT1 = 0x21, 491 DBG_BLOCK_ID_IA = 0x22, 492 DBG_BLOCK_ID_UNUSED3 = 0x23, 493 DBG_BLOCK_ID_SCT0 = 0x24, 494 DBG_BLOCK_ID_SCT1 = 0x25, 495 DBG_BLOCK_ID_SPM0 = 0x26, 496 DBG_BLOCK_ID_SPM1 = 0x27, 497 DBG_BLOCK_ID_TCAA = 0x28, 498 DBG_BLOCK_ID_TCAB = 0x29, 499 DBG_BLOCK_ID_TCCA = 0x2a, 500 DBG_BLOCK_ID_TCCB = 0x2b, 501 DBG_BLOCK_ID_MCC0 = 0x2c, 502 DBG_BLOCK_ID_MCC1 = 0x2d, 503 DBG_BLOCK_ID_MCC2 = 0x2e, 504 DBG_BLOCK_ID_MCC3 = 0x2f, 505 DBG_BLOCK_ID_SX0 = 0x30, 506 DBG_BLOCK_ID_SX1 = 0x31, 507 DBG_BLOCK_ID_SX2 = 0x32, 508 DBG_BLOCK_ID_SX3 = 0x33, 509 DBG_BLOCK_ID_UNUSED4 = 0x34, 510 DBG_BLOCK_ID_UNUSED5 = 0x35, 511 DBG_BLOCK_ID_UNUSED6 = 0x36, 512 DBG_BLOCK_ID_UNUSED7 = 0x37, 513 DBG_BLOCK_ID_PC0 = 0x38, 514 DBG_BLOCK_ID_PC1 = 0x39, 515 DBG_BLOCK_ID_UNUSED8 = 0x3a, 516 DBG_BLOCK_ID_UNUSED9 = 0x3b, 517 DBG_BLOCK_ID_UNUSED10 = 0x3c, 518 DBG_BLOCK_ID_UNUSED11 = 0x3d, 519 DBG_BLOCK_ID_MCB = 0x3e, 520 DBG_BLOCK_ID_UNUSED12 = 0x3f, 521 DBG_BLOCK_ID_SCB0 = 0x40, 522 DBG_BLOCK_ID_SCB1 = 0x41, 523 DBG_BLOCK_ID_UNUSED13 = 0x42, 524 DBG_BLOCK_ID_UNUSED14 = 0x43, 525 DBG_BLOCK_ID_SCF0 = 0x44, 526 DBG_BLOCK_ID_SCF1 = 0x45, 527 DBG_BLOCK_ID_UNUSED15 = 0x46, 528 DBG_BLOCK_ID_UNUSED16 = 0x47, 529 DBG_BLOCK_ID_BCI0 = 0x48, 530 DBG_BLOCK_ID_BCI1 = 0x49, 531 DBG_BLOCK_ID_BCI2 = 0x4a, 532 DBG_BLOCK_ID_BCI3 = 0x4b, 533 DBG_BLOCK_ID_UNUSED17 = 0x4c, 534 DBG_BLOCK_ID_UNUSED18 = 0x4d, 535 DBG_BLOCK_ID_UNUSED19 = 0x4e, 536 DBG_BLOCK_ID_UNUSED20 = 0x4f, 537 DBG_BLOCK_ID_CB00 = 0x50, 538 DBG_BLOCK_ID_CB01 = 0x51, 539 DBG_BLOCK_ID_CB02 = 0x52, 540 DBG_BLOCK_ID_CB03 = 0x53, 541 DBG_BLOCK_ID_CB04 = 0x54, 542 DBG_BLOCK_ID_UNUSED21 = 0x55, 543 DBG_BLOCK_ID_UNUSED22 = 0x56, 544 DBG_BLOCK_ID_UNUSED23 = 0x57, 545 DBG_BLOCK_ID_CB10 = 0x58, 546 DBG_BLOCK_ID_CB11 = 0x59, 547 DBG_BLOCK_ID_CB12 = 0x5a, 548 DBG_BLOCK_ID_CB13 = 0x5b, 549 DBG_BLOCK_ID_CB14 = 0x5c, 550 DBG_BLOCK_ID_UNUSED24 = 0x5d, 551 DBG_BLOCK_ID_UNUSED25 = 0x5e, 552 DBG_BLOCK_ID_UNUSED26 = 0x5f, 553 DBG_BLOCK_ID_TCP0 = 0x60, 554 DBG_BLOCK_ID_TCP1 = 0x61, 555 DBG_BLOCK_ID_TCP2 = 0x62, 556 DBG_BLOCK_ID_TCP3 = 0x63, 557 DBG_BLOCK_ID_TCP4 = 0x64, 558 DBG_BLOCK_ID_TCP5 = 0x65, 559 DBG_BLOCK_ID_TCP6 = 0x66, 560 DBG_BLOCK_ID_TCP7 = 0x67, 561 DBG_BLOCK_ID_TCP8 = 0x68, 562 DBG_BLOCK_ID_TCP9 = 0x69, 563 DBG_BLOCK_ID_TCP10 = 0x6a, 564 DBG_BLOCK_ID_TCP11 = 0x6b, 565 DBG_BLOCK_ID_TCP12 = 0x6c, 566 DBG_BLOCK_ID_TCP13 = 0x6d, 567 DBG_BLOCK_ID_TCP14 = 0x6e, 568 DBG_BLOCK_ID_TCP15 = 0x6f, 569 DBG_BLOCK_ID_TCP16 = 0x70, 570 DBG_BLOCK_ID_TCP17 = 0x71, 571 DBG_BLOCK_ID_TCP18 = 0x72, 572 DBG_BLOCK_ID_TCP19 = 0x73, 573 DBG_BLOCK_ID_TCP20 = 0x74, 574 DBG_BLOCK_ID_TCP21 = 0x75, 575 DBG_BLOCK_ID_TCP22 = 0x76, 576 DBG_BLOCK_ID_TCP23 = 0x77, 577 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 578 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 579 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 580 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 581 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 582 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 583 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 584 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 585 DBG_BLOCK_ID_DB00 = 0x80, 586 DBG_BLOCK_ID_DB01 = 0x81, 587 DBG_BLOCK_ID_DB02 = 0x82, 588 DBG_BLOCK_ID_DB03 = 0x83, 589 DBG_BLOCK_ID_DB04 = 0x84, 590 DBG_BLOCK_ID_UNUSED27 = 0x85, 591 DBG_BLOCK_ID_UNUSED28 = 0x86, 592 DBG_BLOCK_ID_UNUSED29 = 0x87, 593 DBG_BLOCK_ID_DB10 = 0x88, 594 DBG_BLOCK_ID_DB11 = 0x89, 595 DBG_BLOCK_ID_DB12 = 0x8a, 596 DBG_BLOCK_ID_DB13 = 0x8b, 597 DBG_BLOCK_ID_DB14 = 0x8c, 598 DBG_BLOCK_ID_UNUSED30 = 0x8d, 599 DBG_BLOCK_ID_UNUSED31 = 0x8e, 600 DBG_BLOCK_ID_UNUSED32 = 0x8f, 601 DBG_BLOCK_ID_TCC0 = 0x90, 602 DBG_BLOCK_ID_TCC1 = 0x91, 603 DBG_BLOCK_ID_TCC2 = 0x92, 604 DBG_BLOCK_ID_TCC3 = 0x93, 605 DBG_BLOCK_ID_TCC4 = 0x94, 606 DBG_BLOCK_ID_TCC5 = 0x95, 607 DBG_BLOCK_ID_TCC6 = 0x96, 608 DBG_BLOCK_ID_TCC7 = 0x97, 609 DBG_BLOCK_ID_SPS00 = 0x98, 610 DBG_BLOCK_ID_SPS01 = 0x99, 611 DBG_BLOCK_ID_SPS02 = 0x9a, 612 DBG_BLOCK_ID_SPS10 = 0x9b, 613 DBG_BLOCK_ID_SPS11 = 0x9c, 614 DBG_BLOCK_ID_SPS12 = 0x9d, 615 DBG_BLOCK_ID_UNUSED33 = 0x9e, 616 DBG_BLOCK_ID_UNUSED34 = 0x9f, 617 DBG_BLOCK_ID_TA00 = 0xa0, 618 DBG_BLOCK_ID_TA01 = 0xa1, 619 DBG_BLOCK_ID_TA02 = 0xa2, 620 DBG_BLOCK_ID_TA03 = 0xa3, 621 DBG_BLOCK_ID_TA04 = 0xa4, 622 DBG_BLOCK_ID_TA05 = 0xa5, 623 DBG_BLOCK_ID_TA06 = 0xa6, 624 DBG_BLOCK_ID_TA07 = 0xa7, 625 DBG_BLOCK_ID_TA08 = 0xa8, 626 DBG_BLOCK_ID_TA09 = 0xa9, 627 DBG_BLOCK_ID_TA0A = 0xaa, 628 DBG_BLOCK_ID_TA0B = 0xab, 629 DBG_BLOCK_ID_UNUSED35 = 0xac, 630 DBG_BLOCK_ID_UNUSED36 = 0xad, 631 DBG_BLOCK_ID_UNUSED37 = 0xae, 632 DBG_BLOCK_ID_UNUSED38 = 0xaf, 633 DBG_BLOCK_ID_TA10 = 0xb0, 634 DBG_BLOCK_ID_TA11 = 0xb1, 635 DBG_BLOCK_ID_TA12 = 0xb2, 636 DBG_BLOCK_ID_TA13 = 0xb3, 637 DBG_BLOCK_ID_TA14 = 0xb4, 638 DBG_BLOCK_ID_TA15 = 0xb5, 639 DBG_BLOCK_ID_TA16 = 0xb6, 640 DBG_BLOCK_ID_TA17 = 0xb7, 641 DBG_BLOCK_ID_TA18 = 0xb8, 642 DBG_BLOCK_ID_TA19 = 0xb9, 643 DBG_BLOCK_ID_TA1A = 0xba, 644 DBG_BLOCK_ID_TA1B = 0xbb, 645 DBG_BLOCK_ID_UNUSED39 = 0xbc, 646 DBG_BLOCK_ID_UNUSED40 = 0xbd, 647 DBG_BLOCK_ID_UNUSED41 = 0xbe, 648 DBG_BLOCK_ID_UNUSED42 = 0xbf, 649 DBG_BLOCK_ID_TD00 = 0xc0, 650 DBG_BLOCK_ID_TD01 = 0xc1, 651 DBG_BLOCK_ID_TD02 = 0xc2, 652 DBG_BLOCK_ID_TD03 = 0xc3, 653 DBG_BLOCK_ID_TD04 = 0xc4, 654 DBG_BLOCK_ID_TD05 = 0xc5, 655 DBG_BLOCK_ID_TD06 = 0xc6, 656 DBG_BLOCK_ID_TD07 = 0xc7, 657 DBG_BLOCK_ID_TD08 = 0xc8, 658 DBG_BLOCK_ID_TD09 = 0xc9, 659 DBG_BLOCK_ID_TD0A = 0xca, 660 DBG_BLOCK_ID_TD0B = 0xcb, 661 DBG_BLOCK_ID_UNUSED43 = 0xcc, 662 DBG_BLOCK_ID_UNUSED44 = 0xcd, 663 DBG_BLOCK_ID_UNUSED45 = 0xce, 664 DBG_BLOCK_ID_UNUSED46 = 0xcf, 665 DBG_BLOCK_ID_TD10 = 0xd0, 666 DBG_BLOCK_ID_TD11 = 0xd1, 667 DBG_BLOCK_ID_TD12 = 0xd2, 668 DBG_BLOCK_ID_TD13 = 0xd3, 669 DBG_BLOCK_ID_TD14 = 0xd4, 670 DBG_BLOCK_ID_TD15 = 0xd5, 671 DBG_BLOCK_ID_TD16 = 0xd6, 672 DBG_BLOCK_ID_TD17 = 0xd7, 673 DBG_BLOCK_ID_TD18 = 0xd8, 674 DBG_BLOCK_ID_TD19 = 0xd9, 675 DBG_BLOCK_ID_TD1A = 0xda, 676 DBG_BLOCK_ID_TD1B = 0xdb, 677 DBG_BLOCK_ID_UNUSED47 = 0xdc, 678 DBG_BLOCK_ID_UNUSED48 = 0xdd, 679 DBG_BLOCK_ID_UNUSED49 = 0xde, 680 DBG_BLOCK_ID_UNUSED50 = 0xdf, 681 DBG_BLOCK_ID_MCD0 = 0xe0, 682 DBG_BLOCK_ID_MCD1 = 0xe1, 683 DBG_BLOCK_ID_MCD2 = 0xe2, 684 DBG_BLOCK_ID_MCD3 = 0xe3, 685 DBG_BLOCK_ID_MCD4 = 0xe4, 686 DBG_BLOCK_ID_MCD5 = 0xe5, 687 DBG_BLOCK_ID_UNUSED51 = 0xe6, 688 DBG_BLOCK_ID_UNUSED52 = 0xe7, 689 } DebugBlockId_OLD; 690 typedef enum DebugBlockId_BY2 { 691 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 692 DBG_BLOCK_ID_VMC_BY2 = 0x1, 693 DBG_BLOCK_ID_CG_BY2 = 0x2, 694 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 695 DBG_BLOCK_ID_CSC_BY2 = 0x4, 696 DBG_BLOCK_ID_IH_BY2 = 0x5, 697 DBG_BLOCK_ID_SQ_BY2 = 0x6, 698 DBG_BLOCK_ID_GMCON_BY2 = 0x7, 699 DBG_BLOCK_ID_DMA0_BY2 = 0x8, 700 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 701 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 702 DBG_BLOCK_ID_PA0_BY2 = 0xb, 703 DBG_BLOCK_ID_CP0_BY2 = 0xc, 704 DBG_BLOCK_ID_CP2_BY2 = 0xd, 705 DBG_BLOCK_ID_UVDU_BY2 = 0xe, 706 DBG_BLOCK_ID_VCE_BY2 = 0xf, 707 DBG_BLOCK_ID_VGT0_BY2 = 0x10, 708 DBG_BLOCK_ID_IA_BY2 = 0x11, 709 DBG_BLOCK_ID_SCT0_BY2 = 0x12, 710 DBG_BLOCK_ID_SPM0_BY2 = 0x13, 711 DBG_BLOCK_ID_TCAA_BY2 = 0x14, 712 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 713 DBG_BLOCK_ID_MCC0_BY2 = 0x16, 714 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 715 DBG_BLOCK_ID_SX0_BY2 = 0x18, 716 DBG_BLOCK_ID_SX2_BY2 = 0x19, 717 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 718 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 719 DBG_BLOCK_ID_PC0_BY2 = 0x1c, 720 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 721 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 722 DBG_BLOCK_ID_MCB_BY2 = 0x1f, 723 DBG_BLOCK_ID_SCB0_BY2 = 0x20, 724 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 725 DBG_BLOCK_ID_SCF0_BY2 = 0x22, 726 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 727 DBG_BLOCK_ID_BCI0_BY2 = 0x24, 728 DBG_BLOCK_ID_BCI2_BY2 = 0x25, 729 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 730 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 731 DBG_BLOCK_ID_CB00_BY2 = 0x28, 732 DBG_BLOCK_ID_CB02_BY2 = 0x29, 733 DBG_BLOCK_ID_CB04_BY2 = 0x2a, 734 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 735 DBG_BLOCK_ID_CB10_BY2 = 0x2c, 736 DBG_BLOCK_ID_CB12_BY2 = 0x2d, 737 DBG_BLOCK_ID_CB14_BY2 = 0x2e, 738 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 739 DBG_BLOCK_ID_TCP0_BY2 = 0x30, 740 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 741 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 742 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 743 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 744 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 745 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 746 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 747 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 748 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 749 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 750 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 751 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 752 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 753 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 754 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 755 DBG_BLOCK_ID_DB00_BY2 = 0x40, 756 DBG_BLOCK_ID_DB02_BY2 = 0x41, 757 DBG_BLOCK_ID_DB04_BY2 = 0x42, 758 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 759 DBG_BLOCK_ID_DB10_BY2 = 0x44, 760 DBG_BLOCK_ID_DB12_BY2 = 0x45, 761 DBG_BLOCK_ID_DB14_BY2 = 0x46, 762 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 763 DBG_BLOCK_ID_TCC0_BY2 = 0x48, 764 DBG_BLOCK_ID_TCC2_BY2 = 0x49, 765 DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 766 DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 767 DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 768 DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 769 DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 770 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 771 DBG_BLOCK_ID_TA00_BY2 = 0x50, 772 DBG_BLOCK_ID_TA02_BY2 = 0x51, 773 DBG_BLOCK_ID_TA04_BY2 = 0x52, 774 DBG_BLOCK_ID_TA06_BY2 = 0x53, 775 DBG_BLOCK_ID_TA08_BY2 = 0x54, 776 DBG_BLOCK_ID_TA0A_BY2 = 0x55, 777 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 778 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 779 DBG_BLOCK_ID_TA10_BY2 = 0x58, 780 DBG_BLOCK_ID_TA12_BY2 = 0x59, 781 DBG_BLOCK_ID_TA14_BY2 = 0x5a, 782 DBG_BLOCK_ID_TA16_BY2 = 0x5b, 783 DBG_BLOCK_ID_TA18_BY2 = 0x5c, 784 DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 785 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 786 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 787 DBG_BLOCK_ID_TD00_BY2 = 0x60, 788 DBG_BLOCK_ID_TD02_BY2 = 0x61, 789 DBG_BLOCK_ID_TD04_BY2 = 0x62, 790 DBG_BLOCK_ID_TD06_BY2 = 0x63, 791 DBG_BLOCK_ID_TD08_BY2 = 0x64, 792 DBG_BLOCK_ID_TD0A_BY2 = 0x65, 793 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 794 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 795 DBG_BLOCK_ID_TD10_BY2 = 0x68, 796 DBG_BLOCK_ID_TD12_BY2 = 0x69, 797 DBG_BLOCK_ID_TD14_BY2 = 0x6a, 798 DBG_BLOCK_ID_TD16_BY2 = 0x6b, 799 DBG_BLOCK_ID_TD18_BY2 = 0x6c, 800 DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 801 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 802 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 803 DBG_BLOCK_ID_MCD0_BY2 = 0x70, 804 DBG_BLOCK_ID_MCD2_BY2 = 0x71, 805 DBG_BLOCK_ID_MCD4_BY2 = 0x72, 806 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 807 } DebugBlockId_BY2; 808 typedef enum DebugBlockId_BY4 { 809 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 810 DBG_BLOCK_ID_CG_BY4 = 0x1, 811 DBG_BLOCK_ID_CSC_BY4 = 0x2, 812 DBG_BLOCK_ID_SQ_BY4 = 0x3, 813 DBG_BLOCK_ID_DMA0_BY4 = 0x4, 814 DBG_BLOCK_ID_SPIS_BY4 = 0x5, 815 DBG_BLOCK_ID_CP0_BY4 = 0x6, 816 DBG_BLOCK_ID_UVDU_BY4 = 0x7, 817 DBG_BLOCK_ID_VGT0_BY4 = 0x8, 818 DBG_BLOCK_ID_SCT0_BY4 = 0x9, 819 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 820 DBG_BLOCK_ID_MCC0_BY4 = 0xb, 821 DBG_BLOCK_ID_SX0_BY4 = 0xc, 822 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 823 DBG_BLOCK_ID_PC0_BY4 = 0xe, 824 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 825 DBG_BLOCK_ID_SCB0_BY4 = 0x10, 826 DBG_BLOCK_ID_SCF0_BY4 = 0x11, 827 DBG_BLOCK_ID_BCI0_BY4 = 0x12, 828 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 829 DBG_BLOCK_ID_CB00_BY4 = 0x14, 830 DBG_BLOCK_ID_CB04_BY4 = 0x15, 831 DBG_BLOCK_ID_CB10_BY4 = 0x16, 832 DBG_BLOCK_ID_CB14_BY4 = 0x17, 833 DBG_BLOCK_ID_TCP0_BY4 = 0x18, 834 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 835 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 836 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 837 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 838 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 839 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 840 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 841 DBG_BLOCK_ID_DB_BY4 = 0x20, 842 DBG_BLOCK_ID_DB04_BY4 = 0x21, 843 DBG_BLOCK_ID_DB10_BY4 = 0x22, 844 DBG_BLOCK_ID_DB14_BY4 = 0x23, 845 DBG_BLOCK_ID_TCC0_BY4 = 0x24, 846 DBG_BLOCK_ID_TCC4_BY4 = 0x25, 847 DBG_BLOCK_ID_SPS00_BY4 = 0x26, 848 DBG_BLOCK_ID_SPS11_BY4 = 0x27, 849 DBG_BLOCK_ID_TA00_BY4 = 0x28, 850 DBG_BLOCK_ID_TA04_BY4 = 0x29, 851 DBG_BLOCK_ID_TA08_BY4 = 0x2a, 852 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 853 DBG_BLOCK_ID_TA10_BY4 = 0x2c, 854 DBG_BLOCK_ID_TA14_BY4 = 0x2d, 855 DBG_BLOCK_ID_TA18_BY4 = 0x2e, 856 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 857 DBG_BLOCK_ID_TD00_BY4 = 0x30, 858 DBG_BLOCK_ID_TD04_BY4 = 0x31, 859 DBG_BLOCK_ID_TD08_BY4 = 0x32, 860 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 861 DBG_BLOCK_ID_TD10_BY4 = 0x34, 862 DBG_BLOCK_ID_TD14_BY4 = 0x35, 863 DBG_BLOCK_ID_TD18_BY4 = 0x36, 864 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 865 DBG_BLOCK_ID_MCD0_BY4 = 0x38, 866 DBG_BLOCK_ID_MCD4_BY4 = 0x39, 867 } DebugBlockId_BY4; 868 typedef enum DebugBlockId_BY8 { 869 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 870 DBG_BLOCK_ID_CSC_BY8 = 0x1, 871 DBG_BLOCK_ID_DMA0_BY8 = 0x2, 872 DBG_BLOCK_ID_CP0_BY8 = 0x3, 873 DBG_BLOCK_ID_VGT0_BY8 = 0x4, 874 DBG_BLOCK_ID_TCAA_BY8 = 0x5, 875 DBG_BLOCK_ID_SX0_BY8 = 0x6, 876 DBG_BLOCK_ID_PC0_BY8 = 0x7, 877 DBG_BLOCK_ID_SCB0_BY8 = 0x8, 878 DBG_BLOCK_ID_BCI0_BY8 = 0x9, 879 DBG_BLOCK_ID_CB00_BY8 = 0xa, 880 DBG_BLOCK_ID_CB10_BY8 = 0xb, 881 DBG_BLOCK_ID_TCP0_BY8 = 0xc, 882 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 883 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 884 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 885 DBG_BLOCK_ID_DB00_BY8 = 0x10, 886 DBG_BLOCK_ID_DB10_BY8 = 0x11, 887 DBG_BLOCK_ID_TCC0_BY8 = 0x12, 888 DBG_BLOCK_ID_SPS00_BY8 = 0x13, 889 DBG_BLOCK_ID_TA00_BY8 = 0x14, 890 DBG_BLOCK_ID_TA08_BY8 = 0x15, 891 DBG_BLOCK_ID_TA10_BY8 = 0x16, 892 DBG_BLOCK_ID_TA18_BY8 = 0x17, 893 DBG_BLOCK_ID_TD00_BY8 = 0x18, 894 DBG_BLOCK_ID_TD08_BY8 = 0x19, 895 DBG_BLOCK_ID_TD10_BY8 = 0x1a, 896 DBG_BLOCK_ID_TD18_BY8 = 0x1b, 897 DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 898 } DebugBlockId_BY8; 899 typedef enum DebugBlockId_BY16 { 900 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 901 DBG_BLOCK_ID_DMA0_BY16 = 0x1, 902 DBG_BLOCK_ID_VGT0_BY16 = 0x2, 903 DBG_BLOCK_ID_SX0_BY16 = 0x3, 904 DBG_BLOCK_ID_SCB0_BY16 = 0x4, 905 DBG_BLOCK_ID_CB00_BY16 = 0x5, 906 DBG_BLOCK_ID_TCP0_BY16 = 0x6, 907 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 908 DBG_BLOCK_ID_DB00_BY16 = 0x8, 909 DBG_BLOCK_ID_TCC0_BY16 = 0x9, 910 DBG_BLOCK_ID_TA00_BY16 = 0xa, 911 DBG_BLOCK_ID_TA10_BY16 = 0xb, 912 DBG_BLOCK_ID_TD00_BY16 = 0xc, 913 DBG_BLOCK_ID_TD10_BY16 = 0xd, 914 DBG_BLOCK_ID_MCD0_BY16 = 0xe, 915 } DebugBlockId_BY16; 916 typedef enum ColorTransform { 917 DCC_CT_AUTO = 0x0, 918 DCC_CT_NONE = 0x1, 919 ABGR_TO_A_BG_G_RB = 0x2, 920 BGRA_TO_BG_G_RB_A = 0x3, 921 } ColorTransform; 922 typedef enum CompareRef { 923 REF_NEVER = 0x0, 924 REF_LESS = 0x1, 925 REF_EQUAL = 0x2, 926 REF_LEQUAL = 0x3, 927 REF_GREATER = 0x4, 928 REF_NOTEQUAL = 0x5, 929 REF_GEQUAL = 0x6, 930 REF_ALWAYS = 0x7, 931 } CompareRef; 932 typedef enum ReadSize { 933 READ_256_BITS = 0x0, 934 READ_512_BITS = 0x1, 935 } ReadSize; 936 typedef enum DepthFormat { 937 DEPTH_INVALID = 0x0, 938 DEPTH_16 = 0x1, 939 DEPTH_X8_24 = 0x2, 940 DEPTH_8_24 = 0x3, 941 DEPTH_X8_24_FLOAT = 0x4, 942 DEPTH_8_24_FLOAT = 0x5, 943 DEPTH_32_FLOAT = 0x6, 944 DEPTH_X24_8_32_FLOAT = 0x7, 945 } DepthFormat; 946 typedef enum ZFormat { 947 Z_INVALID = 0x0, 948 Z_16 = 0x1, 949 Z_24 = 0x2, 950 Z_32_FLOAT = 0x3, 951 } ZFormat; 952 typedef enum StencilFormat { 953 STENCIL_INVALID = 0x0, 954 STENCIL_8 = 0x1, 955 } StencilFormat; 956 typedef enum CmaskMode { 957 CMASK_CLEAR_NONE = 0x0, 958 CMASK_CLEAR_ONE = 0x1, 959 CMASK_CLEAR_ALL = 0x2, 960 CMASK_ANY_EXPANDED = 0x3, 961 CMASK_ALPHA0_FRAG1 = 0x4, 962 CMASK_ALPHA0_FRAG2 = 0x5, 963 CMASK_ALPHA0_FRAG4 = 0x6, 964 CMASK_ALPHA0_FRAGS = 0x7, 965 CMASK_ALPHA1_FRAG1 = 0x8, 966 CMASK_ALPHA1_FRAG2 = 0x9, 967 CMASK_ALPHA1_FRAG4 = 0xa, 968 CMASK_ALPHA1_FRAGS = 0xb, 969 CMASK_ALPHAX_FRAG1 = 0xc, 970 CMASK_ALPHAX_FRAG2 = 0xd, 971 CMASK_ALPHAX_FRAG4 = 0xe, 972 CMASK_ALPHAX_FRAGS = 0xf, 973 } CmaskMode; 974 typedef enum QuadExportFormat { 975 EXPORT_UNUSED = 0x0, 976 EXPORT_32_R = 0x1, 977 EXPORT_32_GR = 0x2, 978 EXPORT_32_AR = 0x3, 979 EXPORT_FP16_ABGR = 0x4, 980 EXPORT_UNSIGNED16_ABGR = 0x5, 981 EXPORT_SIGNED16_ABGR = 0x6, 982 EXPORT_32_ABGR = 0x7, 983 } QuadExportFormat; 984 typedef enum QuadExportFormatOld { 985 EXPORT_4P_32BPC_ABGR = 0x0, 986 EXPORT_4P_16BPC_ABGR = 0x1, 987 EXPORT_4P_32BPC_GR = 0x2, 988 EXPORT_4P_32BPC_AR = 0x3, 989 EXPORT_2P_32BPC_ABGR = 0x4, 990 EXPORT_8P_32BPC_R = 0x5, 991 } QuadExportFormatOld; 992 typedef enum ColorFormat { 993 COLOR_INVALID = 0x0, 994 COLOR_8 = 0x1, 995 COLOR_16 = 0x2, 996 COLOR_8_8 = 0x3, 997 COLOR_32 = 0x4, 998 COLOR_16_16 = 0x5, 999 COLOR_10_11_11 = 0x6, 1000 COLOR_11_11_10 = 0x7, 1001 COLOR_10_10_10_2 = 0x8, 1002 COLOR_2_10_10_10 = 0x9, 1003 COLOR_8_8_8_8 = 0xa, 1004 COLOR_32_32 = 0xb, 1005 COLOR_16_16_16_16 = 0xc, 1006 COLOR_RESERVED_13 = 0xd, 1007 COLOR_32_32_32_32 = 0xe, 1008 COLOR_RESERVED_15 = 0xf, 1009 COLOR_5_6_5 = 0x10, 1010 COLOR_1_5_5_5 = 0x11, 1011 COLOR_5_5_5_1 = 0x12, 1012 COLOR_4_4_4_4 = 0x13, 1013 COLOR_8_24 = 0x14, 1014 COLOR_24_8 = 0x15, 1015 COLOR_X24_8_32_FLOAT = 0x16, 1016 COLOR_RESERVED_23 = 0x17, 1017 } ColorFormat; 1018 typedef enum SurfaceFormat { 1019 FMT_INVALID = 0x0, 1020 FMT_8 = 0x1, 1021 FMT_16 = 0x2, 1022 FMT_8_8 = 0x3, 1023 FMT_32 = 0x4, 1024 FMT_16_16 = 0x5, 1025 FMT_10_11_11 = 0x6, 1026 FMT_11_11_10 = 0x7, 1027 FMT_10_10_10_2 = 0x8, 1028 FMT_2_10_10_10 = 0x9, 1029 FMT_8_8_8_8 = 0xa, 1030 FMT_32_32 = 0xb, 1031 FMT_16_16_16_16 = 0xc, 1032 FMT_32_32_32 = 0xd, 1033 FMT_32_32_32_32 = 0xe, 1034 FMT_RESERVED_4 = 0xf, 1035 FMT_5_6_5 = 0x10, 1036 FMT_1_5_5_5 = 0x11, 1037 FMT_5_5_5_1 = 0x12, 1038 FMT_4_4_4_4 = 0x13, 1039 FMT_8_24 = 0x14, 1040 FMT_24_8 = 0x15, 1041 FMT_X24_8_32_FLOAT = 0x16, 1042 FMT_RESERVED_33 = 0x17, 1043 FMT_11_11_10_FLOAT = 0x18, 1044 FMT_16_FLOAT = 0x19, 1045 FMT_32_FLOAT = 0x1a, 1046 FMT_16_16_FLOAT = 0x1b, 1047 FMT_8_24_FLOAT = 0x1c, 1048 FMT_24_8_FLOAT = 0x1d, 1049 FMT_32_32_FLOAT = 0x1e, 1050 FMT_10_11_11_FLOAT = 0x1f, 1051 FMT_16_16_16_16_FLOAT = 0x20, 1052 FMT_3_3_2 = 0x21, 1053 FMT_6_5_5 = 0x22, 1054 FMT_32_32_32_32_FLOAT = 0x23, 1055 FMT_RESERVED_36 = 0x24, 1056 FMT_1 = 0x25, 1057 FMT_1_REVERSED = 0x26, 1058 FMT_GB_GR = 0x27, 1059 FMT_BG_RG = 0x28, 1060 FMT_32_AS_8 = 0x29, 1061 FMT_32_AS_8_8 = 0x2a, 1062 FMT_5_9_9_9_SHAREDEXP = 0x2b, 1063 FMT_8_8_8 = 0x2c, 1064 FMT_16_16_16 = 0x2d, 1065 FMT_16_16_16_FLOAT = 0x2e, 1066 FMT_4_4 = 0x2f, 1067 FMT_32_32_32_FLOAT = 0x30, 1068 FMT_BC1 = 0x31, 1069 FMT_BC2 = 0x32, 1070 FMT_BC3 = 0x33, 1071 FMT_BC4 = 0x34, 1072 FMT_BC5 = 0x35, 1073 FMT_BC6 = 0x36, 1074 FMT_BC7 = 0x37, 1075 FMT_32_AS_32_32_32_32 = 0x38, 1076 FMT_APC3 = 0x39, 1077 FMT_APC4 = 0x3a, 1078 FMT_APC5 = 0x3b, 1079 FMT_APC6 = 0x3c, 1080 FMT_APC7 = 0x3d, 1081 FMT_CTX1 = 0x3e, 1082 FMT_RESERVED_63 = 0x3f, 1083 } SurfaceFormat; 1084 typedef enum BUF_DATA_FORMAT { 1085 BUF_DATA_FORMAT_INVALID = 0x0, 1086 BUF_DATA_FORMAT_8 = 0x1, 1087 BUF_DATA_FORMAT_16 = 0x2, 1088 BUF_DATA_FORMAT_8_8 = 0x3, 1089 BUF_DATA_FORMAT_32 = 0x4, 1090 BUF_DATA_FORMAT_16_16 = 0x5, 1091 BUF_DATA_FORMAT_10_11_11 = 0x6, 1092 BUF_DATA_FORMAT_11_11_10 = 0x7, 1093 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 1094 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 1095 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 1096 BUF_DATA_FORMAT_32_32 = 0xb, 1097 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 1098 BUF_DATA_FORMAT_32_32_32 = 0xd, 1099 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 1100 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 1101 } BUF_DATA_FORMAT; 1102 typedef enum IMG_DATA_FORMAT { 1103 IMG_DATA_FORMAT_INVALID = 0x0, 1104 IMG_DATA_FORMAT_8 = 0x1, 1105 IMG_DATA_FORMAT_16 = 0x2, 1106 IMG_DATA_FORMAT_8_8 = 0x3, 1107 IMG_DATA_FORMAT_32 = 0x4, 1108 IMG_DATA_FORMAT_16_16 = 0x5, 1109 IMG_DATA_FORMAT_10_11_11 = 0x6, 1110 IMG_DATA_FORMAT_11_11_10 = 0x7, 1111 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 1112 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 1113 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 1114 IMG_DATA_FORMAT_32_32 = 0xb, 1115 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 1116 IMG_DATA_FORMAT_32_32_32 = 0xd, 1117 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 1118 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 1119 IMG_DATA_FORMAT_5_6_5 = 0x10, 1120 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 1121 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 1122 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 1123 IMG_DATA_FORMAT_8_24 = 0x14, 1124 IMG_DATA_FORMAT_24_8 = 0x15, 1125 IMG_DATA_FORMAT_X24_8_32 = 0x16, 1126 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 1127 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 1128 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 1129 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 1130 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 1131 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 1132 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1133 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1134 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1135 IMG_DATA_FORMAT_GB_GR = 0x20, 1136 IMG_DATA_FORMAT_BG_RG = 0x21, 1137 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1138 IMG_DATA_FORMAT_BC1 = 0x23, 1139 IMG_DATA_FORMAT_BC2 = 0x24, 1140 IMG_DATA_FORMAT_BC3 = 0x25, 1141 IMG_DATA_FORMAT_BC4 = 0x26, 1142 IMG_DATA_FORMAT_BC5 = 0x27, 1143 IMG_DATA_FORMAT_BC6 = 0x28, 1144 IMG_DATA_FORMAT_BC7 = 0x29, 1145 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1146 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1147 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1148 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1149 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1150 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1151 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1152 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1153 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1154 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1155 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1156 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1157 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1158 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1159 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1160 IMG_DATA_FORMAT_4_4 = 0x39, 1161 IMG_DATA_FORMAT_6_5_5 = 0x3a, 1162 IMG_DATA_FORMAT_1 = 0x3b, 1163 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1164 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1165 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1166 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1167 } IMG_DATA_FORMAT; 1168 typedef enum BUF_NUM_FORMAT { 1169 BUF_NUM_FORMAT_UNORM = 0x0, 1170 BUF_NUM_FORMAT_SNORM = 0x1, 1171 BUF_NUM_FORMAT_USCALED = 0x2, 1172 BUF_NUM_FORMAT_SSCALED = 0x3, 1173 BUF_NUM_FORMAT_UINT = 0x4, 1174 BUF_NUM_FORMAT_SINT = 0x5, 1175 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1176 BUF_NUM_FORMAT_FLOAT = 0x7, 1177 } BUF_NUM_FORMAT; 1178 typedef enum IMG_NUM_FORMAT { 1179 IMG_NUM_FORMAT_UNORM = 0x0, 1180 IMG_NUM_FORMAT_SNORM = 0x1, 1181 IMG_NUM_FORMAT_USCALED = 0x2, 1182 IMG_NUM_FORMAT_SSCALED = 0x3, 1183 IMG_NUM_FORMAT_UINT = 0x4, 1184 IMG_NUM_FORMAT_SINT = 0x5, 1185 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1186 IMG_NUM_FORMAT_FLOAT = 0x7, 1187 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1188 IMG_NUM_FORMAT_SRGB = 0x9, 1189 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1190 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1191 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1192 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1193 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1194 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1195 } IMG_NUM_FORMAT; 1196 typedef enum TileType { 1197 ARRAY_COLOR_TILE = 0x0, 1198 ARRAY_DEPTH_TILE = 0x1, 1199 } TileType; 1200 typedef enum NonDispTilingOrder { 1201 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1202 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1203 } NonDispTilingOrder; 1204 typedef enum MicroTileMode { 1205 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1206 ADDR_SURF_THIN_MICRO_TILING = 0x1, 1207 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1208 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1209 ADDR_SURF_THICK_MICRO_TILING = 0x4, 1210 } MicroTileMode; 1211 typedef enum TileSplit { 1212 ADDR_SURF_TILE_SPLIT_64B = 0x0, 1213 ADDR_SURF_TILE_SPLIT_128B = 0x1, 1214 ADDR_SURF_TILE_SPLIT_256B = 0x2, 1215 ADDR_SURF_TILE_SPLIT_512B = 0x3, 1216 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1217 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1218 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1219 } TileSplit; 1220 typedef enum SampleSplit { 1221 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1222 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1223 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1224 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1225 } SampleSplit; 1226 typedef enum PipeConfig { 1227 ADDR_SURF_P2 = 0x0, 1228 ADDR_SURF_P2_RESERVED0 = 0x1, 1229 ADDR_SURF_P2_RESERVED1 = 0x2, 1230 ADDR_SURF_P2_RESERVED2 = 0x3, 1231 ADDR_SURF_P4_8x16 = 0x4, 1232 ADDR_SURF_P4_16x16 = 0x5, 1233 ADDR_SURF_P4_16x32 = 0x6, 1234 ADDR_SURF_P4_32x32 = 0x7, 1235 ADDR_SURF_P8_16x16_8x16 = 0x8, 1236 ADDR_SURF_P8_16x32_8x16 = 0x9, 1237 ADDR_SURF_P8_32x32_8x16 = 0xa, 1238 ADDR_SURF_P8_16x32_16x16 = 0xb, 1239 ADDR_SURF_P8_32x32_16x16 = 0xc, 1240 ADDR_SURF_P8_32x32_16x32 = 0xd, 1241 ADDR_SURF_P8_32x64_32x32 = 0xe, 1242 ADDR_SURF_P8_RESERVED0 = 0xf, 1243 ADDR_SURF_P16_32x32_8x16 = 0x10, 1244 ADDR_SURF_P16_32x32_16x16 = 0x11, 1245 } PipeConfig; 1246 typedef enum NumBanks { 1247 ADDR_SURF_2_BANK = 0x0, 1248 ADDR_SURF_4_BANK = 0x1, 1249 ADDR_SURF_8_BANK = 0x2, 1250 ADDR_SURF_16_BANK = 0x3, 1251 } NumBanks; 1252 typedef enum BankWidth { 1253 ADDR_SURF_BANK_WIDTH_1 = 0x0, 1254 ADDR_SURF_BANK_WIDTH_2 = 0x1, 1255 ADDR_SURF_BANK_WIDTH_4 = 0x2, 1256 ADDR_SURF_BANK_WIDTH_8 = 0x3, 1257 } BankWidth; 1258 typedef enum BankHeight { 1259 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1260 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1261 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1262 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1263 } BankHeight; 1264 typedef enum BankWidthHeight { 1265 ADDR_SURF_BANK_WH_1 = 0x0, 1266 ADDR_SURF_BANK_WH_2 = 0x1, 1267 ADDR_SURF_BANK_WH_4 = 0x2, 1268 ADDR_SURF_BANK_WH_8 = 0x3, 1269 } BankWidthHeight; 1270 typedef enum MacroTileAspect { 1271 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1272 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1273 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1274 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1275 } MacroTileAspect; 1276 typedef enum GATCL1RequestType { 1277 GATCL1_TYPE_NORMAL = 0x0, 1278 GATCL1_TYPE_SHOOTDOWN = 0x1, 1279 GATCL1_TYPE_BYPASS = 0x2, 1280 } GATCL1RequestType; 1281 typedef enum TCC_CACHE_POLICIES { 1282 TCC_CACHE_POLICY_LRU = 0x0, 1283 TCC_CACHE_POLICY_STREAM = 0x1, 1284 } TCC_CACHE_POLICIES; 1285 typedef enum MTYPE { 1286 MTYPE_NC_NV = 0x0, 1287 MTYPE_NC = 0x1, 1288 MTYPE_CC = 0x2, 1289 MTYPE_UC = 0x3, 1290 } MTYPE; 1291 typedef enum PERFMON_COUNTER_MODE { 1292 PERFMON_COUNTER_MODE_ACCUM = 0x0, 1293 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1294 PERFMON_COUNTER_MODE_MAX = 0x2, 1295 PERFMON_COUNTER_MODE_DIRTY = 0x3, 1296 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1297 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1298 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1299 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1300 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1301 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1302 PERFMON_COUNTER_MODE_RESERVED = 0xf, 1303 } PERFMON_COUNTER_MODE; 1304 typedef enum PERFMON_SPM_MODE { 1305 PERFMON_SPM_MODE_OFF = 0x0, 1306 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1307 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1308 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1309 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1310 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1311 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1312 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1313 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1314 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1315 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1316 } PERFMON_SPM_MODE; 1317 typedef enum SurfaceTiling { 1318 ARRAY_LINEAR = 0x0, 1319 ARRAY_TILED = 0x1, 1320 } SurfaceTiling; 1321 typedef enum SurfaceArray { 1322 ARRAY_1D = 0x0, 1323 ARRAY_2D = 0x1, 1324 ARRAY_3D = 0x2, 1325 ARRAY_3D_SLICE = 0x3, 1326 } SurfaceArray; 1327 typedef enum ColorArray { 1328 ARRAY_2D_ALT_COLOR = 0x0, 1329 ARRAY_2D_COLOR = 0x1, 1330 ARRAY_3D_SLICE_COLOR = 0x3, 1331 } ColorArray; 1332 typedef enum DepthArray { 1333 ARRAY_2D_ALT_DEPTH = 0x0, 1334 ARRAY_2D_DEPTH = 0x1, 1335 } DepthArray; 1336 typedef enum ENUM_NUM_SIMD_PER_CU { 1337 NUM_SIMD_PER_CU = 0x4, 1338 } ENUM_NUM_SIMD_PER_CU; 1339 1340 #endif /* OSS_2_4_ENUM_H */ 1341