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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dmc_regs.h12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
14 #define _PIPEDMC_CONTROL_A 0x45250
15 #define _PIPEDMC_CONTROL_B 0x45254
19 #define PIPEDMC_ENABLE REG_BIT(0)
21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
24 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
25 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
30 0x400 * ((dmc_id) - 1))
32 #define __DMC_REG_MMIO_BASE 0x8f000
43 #define _DMC_EVT_HTP_0 0x8f004
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/msm/
Dqcom,qcm2290-dpu.yaml61 reg = <0x05e01000 0x8f000>,
62 <0x05eb0000 0x2008>;
76 interrupts = <0>;
80 #size-cells = <0>;
82 port@0 {
83 reg = <0>;
Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
Dqcom,sc7280-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
Dqcom,sm8150-dpu.yaml54 reg = <0x0ae01000 0x8f000>,
55 <0x0aeb0000 0x2008>;
71 interrupts = <0>;
75 #size-cells = <0>;
77 port@0 {
78 reg = <0>;
Dqcom,sdm845-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
75 interrupts = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
Dqcom,sm8250-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
78 interrupts = <0>;
82 #size-cells = <0>;
84 port@0 {
85 reg = <0>;
Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
Dqcom,sc8280xp-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
87 interrupts = <0>;
91 #size-cells = <0>;
93 port@0 {
94 reg = <0>;
Dqcom,sm8550-dpu.yaml64 reg = <0x0ae01000 0x8f000>,
65 <0x0aeb0000 0x2008>;
88 interrupts = <0>;
92 #size-cells = <0>;
94 port@0 {
95 reg = <0>;
Dqcom,sm8350-dpu.yaml58 reg = <0x0ae01000 0x8f000>,
59 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
86 #size-cells = <0>;
88 port@0 {
89 reg = <0>;
Dqcom,sm8650-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
84 interrupts = <0>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
Dqcom,sm7150-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
86 interrupts = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
Dqcom,sm8450-dpu.yaml65 reg = <0x0ae01000 0x8f000>,
66 <0x0aeb0000 0x2008>;
89 interrupts = <0>;
93 #size-cells = <0>;
95 port@0 {
96 reg = <0>;
Dqcom,sc8280xp-mdss.yaml35 "^display-controller@[0-9a-f]+$":
43 "^displayport-controller@[0-9a-f]+$":
65 reg = <0x0ae00000 0x1000>;
83 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
84 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
87 iommus = <&apps_smmu 0x1000 0x402>;
95 reg = <0x0ae01000 0x8f000>,
96 <0x0aeb0000 0x2008>;
119 interrupts = <0>;
123 #size-cells = <0>;
[all …]
Dqcom,sm6115-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
90 reg = <0x05e00000 0x1000>;
101 iommus = <&apps_smmu 0x420 0x2>,
102 <&apps_smmu 0x421 0x0>;
107 reg = <0x05e01000 0x8f000>,
108 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
[all …]
Dqcom,qcm2290-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
93 reg = <0x05e00000 0x1000>;
110 iommus = <&apps_smmu 0x420 0x2>,
111 <&apps_smmu 0x421 0x0>;
116 reg = <0x05e01000 0x8f000>,
117 <0x05eb0000 0x2008>;
131 interrupts = <0>;
135 #size-cells = <0>;
[all …]
Dqcom,x1e80100-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^phy@[0-9a-f]+$":
74 reg = <0x0ae00000 0x1000>;
77 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
78 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
79 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
95 iommus = <&apps_smmu 0x1c00 0x2>;
103 reg = <0x0ae01000 0x8f000>,
104 <0x0aeb0000 0x2008>;
[all …]
Dqcom,sm6350-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
109 iommus = <&apps_smmu 0x800 0x2>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
145 #size-cells = <0>;
[all …]
Dqcom,sm8350-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
99 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
100 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
112 iommus = <&apps_smmu 0x820 0x402>;
124 reg = <0x0ae01000 0x8f000>,
125 <0x0aeb0000 0x2008>;
[all …]
Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
Dqcom,msm8998-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
79 reg = <0x0c900000 0x1000>;
93 iommus = <&mmss_smmu 0>;
100 reg = <0x0c901000 0x8f000>,
101 <0x0c9a8e00 0xf0>,
102 <0x0c9b0000 0x2008>,
103 <0x0c9b8000 0x1040>;
114 interrupts = <0>;
[all …]
Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
Dqcom,sm8650-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
97 iommus = <&apps_smmu 0x1c00 0x2>;
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
[all …]

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